sngks32csio.h

内有4510等好几个bsp

/* sngks32cSio.h - header file for Samsung KS32C serial driver */

/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01c,16jul02,m_h  C++ protection
01b,26apr01,m_h  convert tabs to spaces for readability
01a,12apr01,m_h  created from snds100 template.
*/

#ifndef __INCsngks32cSioh
#define __INCsngks32cSioh

#ifdef __cplusplus
extern "C" {
#endif

#include "sioLib.h"
#include "sngks32c.h"


/* Register offsets from Base Address*/

#define SNGKS32C_ULCON         0x0000        /*UART Line Control Registers*/
#define SNGKS32C_UCON          0x0004        /*UART Control Register */
#define SNGKS32C_USTAT         0x0008        /*UART Status Register */
#define SNGKS32C_UTXBUF        0x000c        /*UART Transmit Buffer Register*/
#define SNGKS32C_URXBUF        0x0010        /*UART Receive Buffer Register*/
#define SNGKS32C_UBRDIV        0x0014        /*UART Baud Rate Divisor Register*/
#define SNGKS32C_BRDCNT        0x0018        /*UART Baud Rate Count Register */
#define SNGKS32C_BRDCLK        0x001c        /*UART Baud Rate Clock Monitor*/



/* Bit definitions within ULCON0/1 Line Control Register*/

#define PARITY_NONE     0x00            /* Set No Parity*/
#define PARITY_ODD      0x20            /* Set Odd Parity*/
#define PARITY_EVEN     0x28            /* Set Even Parity*/
#define ONE_STOP        0x00            /* One Stop Bit*/
#define WORD_LEN        0x03            /* Set Word Length 8*/
#define INT_CLK         0x00            /* Internal Clock Mode */
#define    EXT_CLK      0x40            /* External Clock Mode */


/* Bit definitions within UCON0/1 Control Register*/

#define UCON_RX          0x01            /* Receive Mode -Interrupt*/
#define UCON_STAT_EN     0x04            /* Status Interrrupt -Enable*/
#define UCON_TX          0x08            /* Transmit Mode-Interrupt*/
#define UCON_TX_DIS      0x01            /* Transmit Interrupt -Disable*/
#define UCON_DSR         0x20            /* Data Set Ready -Enable*/
#define UCON_BREAK       0x40            /* Set Break*/
#define UCON_RX_TX_RESET 0xe4            /* Rx and Tx Reset */

/* Bit definitions within USTAT0/1 Status Register*/

#define USTAT_DTR_LOW   0x10            /* DTR Enable */
#define USTAT_DTR_HIGH  0x00            /* DTR Disable*/
#define USTAT_TX_READY  0x40            /* Transmitter Ready for another char */
#define USTAT_RX_AVAIL  0x20            /* Character has arrived*/ 
#define USTAT_OVER_ERR  0x01            /* Over Run Error*/
#define USTAT_PAR_ERR   0x02            /* Parity Error*/
#define USTAT_FRAME_ERR 0x04            /* Frame Error*/ 
#define USTAT_RX_READY  0x20            /* Receive Data Buffer*/



/* UART Baud Rate Divisor Time Constant Value (MCLK2 = 25MHz) */

#define SNGKS32C_CNT0_1200   (1301<<4)    /* Baud_Rate 1200*/
#define SNGKS32C_CNT0_2400    (650<<4)    /* Baud_Rate 2400*/
#define SNGKS32C_CNT0_4800    (324<<4)    /* Baud_Rate 4800*/
#define SNGKS32C_CNT0_9600    (162<<4)    /* Baud_Rate 9600*/
#define SNGKS32C_CNT0_19200    (80<<4)    /* Baud_Rate 19200*/
#define SNGKS32C_CNT0_38400    (40<<4)    /* Baud_Rate 38400*/
#define SNGKS32C_CNT0_57600    (26<<4)    /* Baud_Rate 57600*/
#define SNGKS32C_CNT0_115200   (13<<4)    /* Baud_Rate 115200*/
#define SNGKS32C_CNT0_230400    (6<<4)    /* Baud_Rate 230400*/
#define SNGKS32C_CNT0_460800    (2<<4)    /* Baud_Rate 460800*/

#define SNGKS32C_CNT1_VAL         0x00    /* Baud Rate Divisor Value*/


/* device and channel structures */

typedef struct
    {
    /* must be first */

    SIO_CHAN        sio;        /* standard SIO_CHAN element */

    /* callbacks */

    STATUS            (*getTxChar) (void *, ...);
    STATUS            (*putRcvChar) (void *, ...);
    void *            getTxArg;
    void *            putRcvArg;

    /* register addresses */

    UINT32 *          regs;        /*UART Registers*/

    /*  interrupts */
    UINT8             intLevelRx;     /* recv interrupt Level for this device*/
    UINT8             intLevelTx;     /* transmit interrupt Level for this device*/
  

    /* misc */
    UINT32            regDelta;       /* register address spacing */
    uint_t            options;        /* Hardware options */
    int               mode;           /* current mode (interrupt or poll) */
    int               baudRate;       /* input clock frequency */

    } SNGKS32C_CHAN;

/* function prototypes */

#if defined(__STDC__)

extern void    sngks32cDevInit  (SNGKS32C_CHAN *pChan); 
extern void    sngks32cDevInit2 (SNGKS32C_CHAN *pChan); 
extern void    sngks32cIntRcv   (SNGKS32C_CHAN *pChan);
extern void    sngks32cIntTx    (SNGKS32C_CHAN *pChan);

#else   /* __STDC__ */

extern void    sngks32cDevInit  ();
extern void    sngks32cDevInit2 ();
extern void    sngks32cIntRcv   ();
extern void    sngks32cIntTx    ();


#endif  /* __STDC__ */

#ifdef __cplusplus
}
#endif

#endif  /* __INCsngks32cSioh */