stm8l15x_tim1.c

STM8L的tim4定时器使用

  TIM1->CCR2L = (uint8_t)(TIM1_Pulse);
}

/**
  * @brief  Initializes the TIM1 Channel3 according to the specified parameters.
  * @param  TIM1_OCMode specifies the Output Compare mode
  *          This parameter can be one of the following values:
  *            @arg TIM1_OCMode_Timing: OC Mode Timing
  *            @arg TIM1_OCMode_Active: OC Mode Active
  *            @arg TIM1_OCMode_Inactive: OC Mode Inactive
  *            @arg TIM1_OCMode_Toggle: OC Mode Toggle
  *            @arg TIM1_OCMode_PWM1: OC Mode PWM1
  *            @arg TIM1_OCMode_PWM2: OC Mode PWM2     
  * @param  TIM1_OutputState specifies the Output State
  *          This parameter can be one of the following values:
  *            @arg TIM1_OutputState_Disable: Output state disable
  *            @arg TIM1_OutputState_Enable: Output state enable
  * @param  TIM1_OutputNState specifies the Complementary Output State
  *          This parameter can be one of the following values:
  *            @arg TIM1_OutputNState_Disable: Output N state disable
  *            @arg TIM1_OutputNState_Enable: Output N state enable
  * @param  TIM1_Pulse specifies the Pulse width value.
  * @param  TIM1_OCPolarity specifies the Output Compare Polarity
  *          This parameter can be one of the following values:
  *            @arg TIM1_OCPolarity_High: Output Compare active low
  *            @arg TIM1_OCPolarity_Low: Output Compare active high
  * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity
  *          This parameter can be one of the following values:
  *            @arg TIM1_OCNPolarity_High: Complementary Output Compare active low
  *            @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high
  * @param  TIM1_OCIdleState specifies the Output Compare Idle State
  *          This parameter can be one of the following values:
  *            @arg TIM1_OCIdleState_Set: Output Compare Idle state set
  *            @arg TIM1_OCIdleState_Reset: Output Compare Idle state reset
  * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle State
  *          This parameter can be one of the following values:
  *            @arg TIM1_OCNIdleState_Set: Complementary Output Compare Idle state set
  *            @arg TIM1_OCNIdleState_Reset: Complementary Output Compare Idle state reset
  * @retval None
  */
void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
                  TIM1_OutputState_TypeDef TIM1_OutputState,
                  TIM1_OutputNState_TypeDef TIM1_OutputNState,
                  uint16_t TIM1_Pulse,
                  TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
                  TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
                  TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
                  TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
{

  /* Check the parameters */
  assert_param(IS_TIM1_OC_MODE(TIM1_OCMode));
  assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OutputState));
  assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OutputNState));
  assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
  assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity));
  assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCIdleState));
  assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCNIdleState));

  /* Disable the Channel 1: Reset the CCE Bit, Set the Output State,
     the Output N State, the Output Polarity & the Output N Polarity */
  TIM1->CCER2 &= (uint8_t)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));

  /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */
  TIM1->CCER2 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER2_CC3E) | (uint8_t)(TIM1_OutputNState & TIM1_CCER2_CC3NE))
                           | (uint8_t)((uint8_t)(TIM1_OCPolarity & TIM1_CCER2_CC3P) | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER2_CC3NP)));

  /* Reset the Output Compare Bits & Set the Output Compare Mode */
  TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);

  /* Reset the Output Idle state & the Output N Idle state bits */
  TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
  /* Set the Output Idle state & the Output N Idle state configuration */
  TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS3 & TIM1_OCIdleState) | (uint8_t) (TIM1_OISR_OIS3N & TIM1_OCNIdleState));

  /* Set the Pulse value */
  TIM1->CCR3H = (uint8_t)(TIM1_Pulse >> 8);
  TIM1->CCR3L = (uint8_t)(TIM1_Pulse);
}

/**
  * @brief  Configures the Break feature, dead time, Lock level, the OSSI,
  *         and the AOE(automatic output enable).
  * @param  TIM1_OSSIState specifies the OSSIS State
  *          This parameter can be one of the following values:
  *            @arg TIM1_OSSIState_Enable: OSSIS State enabled
  *            @arg TIM1_OSSIState_Disable: OSSIS State disabled   
  * @param  TIM1_LockLevel specifies the lock level
  *          This parameter can be one of the following values:
  *            @arg TIM1_LockLevel_Off: No lock level
  *            @arg TIM1_LockLevel_1: Lock level 1  
  *            @arg TIM1_LockLevel_2: Lock level 2
  *            @arg TIM1_LockLevel_3: Lock level 3
  * @param  TIM1_DeadTime specifies the dead time value.
  * @param  TIM1_Break specifies the Break state
  *          This parameter can be one of the following values:
  *            @arg TIM1_BreakState_Enable: Break enabled
  *            @arg TIM1_BreakState_Disable: Break disabled  
  * @param  TIM1_BreakPolarity specifies the Break polarity
  *          This parameter can be one of the following values:
  *            @arg TIM1_BreakPolarity_Low: Break polarity high
  *            @arg TIM1_BreakPolarity_High: Break polarity low
  * @param  TIM1_AutomaticOutput specifies the Automatic Output configuration
  *          This parameter can be one of the following values:
  *            @arg TIM1_AutomaticOutput_Enable: Automatic Output enabled
  *            @arg TIM1_AutomaticOutput_Disable: Automatic Output disabled  
  * @retval None
  */
void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
                     TIM1_LockLevel_TypeDef TIM1_LockLevel,
                     uint8_t TIM1_DeadTime,
                     TIM1_BreakState_TypeDef TIM1_Break,
                     TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
                     TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
{

  /* Check the parameters */
  assert_param(IS_TIM1_OSSI_STATE(TIM1_OSSIState));
  assert_param(IS_TIM1_LOCK_LEVEL(TIM1_LockLevel));
  assert_param(IS_TIM1_BREAK_STATE(TIM1_Break));
  assert_param(IS_TIM1_BREAK_POLARITY(TIM1_BreakPolarity));
  assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_AutomaticOutput));

  TIM1->DTR = (uint8_t)(TIM1_DeadTime);
  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSI State,
     the dead time value  and the Automatic Output Enable Bit */

  TIM1->BKR  =  (uint8_t)((uint8_t)((uint8_t)TIM1_OSSIState | (uint8_t)TIM1_LockLevel)
                          | (uint8_t)((uint8_t)((uint8_t)TIM1_Break | (uint8_t)TIM1_BreakPolarity)
                                      | (uint8_t)TIM1_AutomaticOutput));

}

/**
  * @brief  Enables or disables the TIM1 peripheral Main Outputs.
  * @param  NewState new state of the TIM1 peripheral. 
  *          This parameter can be ENABLE or DISABLE.
  * @retval None
  */
void TIM1_CtrlPWMOutputs(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  /* Set or Reset the MOE Bit */

  if (NewState != DISABLE)
  {
    TIM1->BKR |= TIM1_BKR_MOE;
  }
  else
  {
    TIM1->BKR &= (uint8_t)(~TIM1_BKR_MOE);
  }
}

/**
  * @brief  Selects the TIM1 Output Compare Mode. This function disables the
  *         selected channel before changing the Output Compare Mode. 
  * @note   User has to enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.
  * @param  TIM1_Channel specifies the TIM1 Channel.
  *          This parameter can be one of the following values:
  *            @arg TIM1_Channel_1: TIM1 Channel1
  *            @arg TIM1_Channel_2: TIM1 Channel2
  *            @arg TIM1_Channel_3: TIM1 Channel3
  *            @arg TIM1_Channel_4: TIM1 Channel4
  * @param  TIM1_OCMode specifies the TIM1 Output Compare Mode.
  *          This parameter can be one of the following values:
  *            @arg TIM1_OCMode_Timing: OC Mode Timing
  *            @arg TIM1_OCMode_Active: OC Mode Active
  *            @arg TIM1_OCMode_Inactive: OC Mode Inactive
  *            @arg TIM1_OCMode_Toggle: OC Mode Toggle
  *            @arg TIM1_OCMode_PWM1: OC Mode PWM1
  *            @arg TIM1_OCMode_PWM2: OC Mode PWM2  
  * @retval None
  */
void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
{
  /* Check the parameters */
  assert_param(IS_TIM1_CHANNEL(TIM1_Channel));
  assert_param(IS_TIM1_OCM(TIM1_OCMode));

  if (TIM1_Channel == TIM1_Channel_1)
  {
    /* Disable the Channel 1: Reset the CCE Bit */
    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);

    /* Reset the Output Compare Bits & Set the Output Compare Mode */
    TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);
  }
  else if (TIM1_Channel == TIM1_Channel_2)
  {
    /* Disable the Channel 2: Reset the CCE Bit */
    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);

    /* Reset the Output Compare Bits & Set the Output Compare Mode */
    TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);
  }
  else
  {
    /* Disable the Channel 3: Reset the CCE Bit */
    TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);

    /* Reset the Output Compare Bits & Set the Output Compare Mode */
    TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);

  }
}

/**
  * @brief  Sets the TIM1 Capture Compare1 Register value.
  * @param  Compare1 specifies the Capture Compare1 register new value.
  *          This parameter is between 0x0000 and 0xFFFF.
  * @retval None
  */
void TIM1_SetCompare1(uint16_t Compare1)
{
  /* Set the Capture Compare1 Register value */
  TIM1->CCR1H = (uint8_t)(Compare1 >> 8);
  TIM1->CCR1L = (uint8_t)(Compare1);

}

/**
  * @brief  Sets the TIM1 Capture Compare2 Register value.
  * @param  Compare2 specifies the Capture Compare2 register new value.
  *          This parameter is between 0x0000 and 0xFFFF.
  * @retval None
  */
void TIM1_SetCompare2(uint16_t Compare2)
{
  /* Set the Capture Compare2 Register value */
  TIM1->CCR2H = (uint8_t)(Compare2 >> 8);
  TIM1->CCR2L = (uint8_t)(Compare2);
}

/**
  * @brief  Sets the TIM1 Capture Compare3 Register value.
  * @param  Compare3 specifies the Capture Compare3 register new value.
  *          This parameter is between 0x0000 and 0xFFFF.
  * @retval None
  */
void TIM1_SetCompare3(uint16_t Compare3)
{
  /* Set the Capture Compare3 Register value */
  TIM1->CCR3H = (uint8_t)(Compare3 >> 8);
  TIM1->CCR3L = (uint8_t)(Compare3);
}

/**
  * @brief  Sets the TIM1 Capture Compare4 Register value.
  * @param  Compare4 specifies the Capture Compare4 register new value.
  *          This parameter is between 0x0000 and 0xFFFF.
  * @retval None
  */
void TIM1_SetCompare4(uint16_t Compare4)
{
  /* Set the Capture Compare4 Register value */
  TIM1->CCR4H = (uint8_t)(Compare4 >> 8);
  TIM1->CCR4L = (uint8_t)(Compare4);
}

/**
  * @brief  Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
  * @param  NewState new state of the Capture Compare Preload Control bit.
  *          This parameter can be ENABLE or DISABLE.
  * @retval None
  */
void TIM1_CCPreloadControl(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  /* Set or Reset the CCPC Bit */
  if (NewState != DISABLE)
  {
    TIM1->CR2 |= TIM1_CR2_CCPC;
  }
  else
  {
    TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCPC);
  }
}

/**
  * @brief  Forces the TIM1 Channel1 output waveform to active or inactive level.
  * @param  TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
  *          This parameter can be one of the following values:
  *            @arg TIM1_ForcedAction_Active: Force active level on OC1REF
  *            @arg TIM1_ForcedAction_Inactive: Force inactive level on OC1REF.
  * @retval None
  */
void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
{
  /* Check the parameters */
  assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));

  /* Reset the OCM Bits & Configure the Forced output Mode */
  TIM1->CCMR1 =  (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction);
}

/**
  * @brief  Forces the TIM1 Channel2 output waveform to active or inactive level.
  * @param  TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
  *          This parameter can be one of the following values:
  *            @arg TIM1_ForcedAction_Active: Force active level on OC2REF
  *            @arg TIM1_ForcedAction_Inactive: Force inactive level on OC2REF.
  * @retval None
  */
void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
{
  /* Check the parameters */
  assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));

  /* Reset the OCM Bits & Configure the Forced output Mode */
  TIM1->CCMR2  =  (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction);
}

/**
  * @brief  Forces the TIM1 Channel3 output waveform to active or inactive level.
  * @param  TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
  *          This parameter can be one of the following values:
  *            @arg TIM1_ForcedAction_Active: Force active level on OC3REF
  *            @arg TIM1_ForcedAction_Inactive: Force inactive level on OC3REF.
  * @retval None
  */
void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
{
  /* Check the parameters */
  assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));

  /* Reset the OCM Bits */ /* Configure The Forced output Mode */
  TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction);
}

/**
  * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR1.
  * @param  NewState new state of the Capture Compare Preload register.
  *          This parameter can be ENABLE or DISABLE.
  * @retval None
  */
void TIM1_OC1PreloadConfig(FunctionalState NewState)
{
  /* Check the parameters */