📄 stm8l15x_usart.c
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In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
In this Mode it is advised to use the following function:
- void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified USART interrupts.
* @param USARTx: where x can be 1 to select the specified USART peripheral.
* @param USART_IT specifies the USART interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
* @arg USART_IT_OR: Overrun error interrupt
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_ERR: Error interrupt
* @param NewState new state of the specified USART interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT, FunctionalState NewState)
{
uint8_t usartreg, itpos = 0x00;
assert_param(IS_USART_CONFIG_IT(USART_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Get the USART register index */
usartreg = (uint8_t)((uint16_t)USART_IT >> 0x08);
/* Get the USART IT index */
itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
if (NewState != DISABLE)
{
/**< Enable the Interrupt bits according to USART_IT mask */
if (usartreg == 0x01)
{
USARTx->CR1 |= itpos;
}
else if (usartreg == 0x05)
{
USARTx->CR5 |= itpos;
}
/*uartreg =0x02*/
else
{
USARTx->CR2 |= itpos;
}
}
else
{
/**< Disable the interrupt bits according to USART_IT mask */
if (usartreg == 0x01)
{
USARTx->CR1 &= (uint8_t)(~itpos);
}
else if (usartreg == 0x05)
{
USARTx->CR5 &= (uint8_t)(~itpos);
}
/*uartreg =0x02*/
else
{
USARTx->CR2 &= (uint8_t)(~itpos);
}
}
}
/**
* @brief Checks whether the specified USART flag is set or not.
* @param USARTx: Select the USARTx peripheral.
* @param USART_FLAG specifies the flag to check.
* This parameter can be one of the following values:
* @arg USART_FLAG_TXE: Transmit Data Register empty
* @arg USART_FLAG_TC: Transmission Complete
* @arg USART_FLAG_RXNE: Read Data Register Not Empty
* @arg USART_FLAG_IDLE: Idle line detected
* @arg USART_FLAG_OR: OverRun error
* @arg USART_FLAG_NF: Noise error
* @arg USART_FLAG_FE: Framing Error
* @arg USART_FLAG_PE: Parity Error
* @arg USART_FLAG_SBK: Send Break characters
* @retval FlagStatus (SET or RESET)
*/
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
{
FlagStatus status = RESET;
/* Check parameters */
assert_param(IS_USART_FLAG(USART_FLAG));
if (USART_FLAG == USART_FLAG_SBK)
{
if ((USARTx->CR2 & (uint8_t)USART_FLAG) != (uint8_t)0x00)
{
/* USART_FLAG is set*/
status = SET;
}
else
{
/* USART_FLAG is reset*/
status = RESET;
}
}
else
{
if ((USARTx->SR & (uint8_t)USART_FLAG) != (uint8_t)0x00)
{
/* USART_FLAG is set*/
status = SET;
}
else
{
/* USART_FLAG is reset*/
status = RESET;
}
}
/* Return the USART_FLAG status*/
return status;
}
/**
* @brief Clears the USARTx's pending flags.
* @param USARTx: where x can be 1 to select the specified USART peripheral.
* @param USART_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg USART_FLAG_TC: Transmission Complete flag.
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
* @note PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error)
* and IDLE (Idle line detected) flags are cleared by software sequence: a read
* operation to USART_SR register (USART_GetFlagStatus())followed by a read
* operation to USART_DR register(USART_ReceiveData8() or USART_ReceiveData9()).
* @note RXNE flag can be also cleared by a read to the USART_DR register
* (USART_ReceiveData8()or USART_ReceiveData9()).
* @note TC flag can be also cleared by software sequence: a read operation to USART_SR
* register (USART_GetFlagStatus()) followed by a write operation to USART_DR
* register (USART_SendData8() or USART_SendData9()).
* @note TXE flag is cleared only by a write to the USART_DR register
* (USART_SendData8() or USART_SendData9()).
* @note SBK flag is cleared during the stop bit of break.
* @retval None
*/
void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
{
/* Check the parameters */
assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
/*< Clear RXNE or TC flags */
USARTx->SR = (uint8_t)((uint16_t)~((uint16_t)USART_FLAG));
}
/**
* @brief Checks whether the specified USART interrupt has occurred or not.
* @param USARTx: where x can be 1 to select the specified USART peripheral.
* @param USART_IT: Specifies the USART interrupt pending bit to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_OR: OverRun Error interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @arg USART_IT_FE: Frame Error interrupt
* @arg USART_IT_NF: Noise Flag Error interrupt
* @retval ITStatus The new state of USART_IT (SET or RESET).
*/
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
{
ITStatus pendingbitstatus = RESET;
uint8_t temp = 0;
uint8_t itpos = 0;
uint8_t itmask1 = 0;
uint8_t itmask2 = 0;
uint8_t enablestatus = 0;
/* Check parameters */
assert_param(IS_USART_GET_IT(USART_IT));
/* Get the USART IT index */
itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
/* Get the USART IT index */
itmask1 = (uint8_t)((uint8_t)USART_IT >> (uint8_t)4);
/* Set the IT mask*/
itmask2 = (uint8_t)((uint8_t)1 << itmask1);
/* Check the status of the specified USART pending bit*/
if (USART_IT == USART_IT_PE)
{
/* Get the USART_IT enable bit status*/
enablestatus = (uint8_t)((uint8_t)USARTx->CR1 & itmask2);
/* Check the status of the specified USART interrupt*/
if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
{
/* Interrupt occurred*/
pendingbitstatus = SET;
}
else
{
/* Interrupt not occurred*/
pendingbitstatus = RESET;
}
}
else if (USART_IT == USART_IT_OR)
{
/* Get the USART_IT enable bit status*/
enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
/* Check the status of the specified USART interrupt*/
temp = (uint8_t)(USARTx->CR5 & USART_CR5_EIE);
if (( (USARTx->SR & itpos) != 0x00) && ((enablestatus || temp)))
{
/* Interrupt occurred*/
pendingbitstatus = SET;
}
else
{
/* Interrupt not occurred*/
pendingbitstatus = RESET;
}
}
else
{
/* Get the USART_IT enable bit status*/
enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
/* Check the status of the specified USART interrupt*/
if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
{
/* Interrupt occurred*/
pendingbitstatus = SET;
}
else
{
/* Interrupt not occurred*/
pendingbitstatus = RESET;
}
}
/* Return the USART_IT status*/
return pendingbitstatus;
}
/**
* @brief Clears the USARTx抯 interrupt pending bits.
* @param USARTx: where x can be 1 to select the specified USART peripheral.
* @param USART_IT: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg USART_IT_RXNE: Receive Data register not empty interrupt.
* @arg USART_IT_TC: Transmission complete interrupt.
* @note PE (Parity error), FE (Framing error), NE (Noise error),
* OR (OverRun error) and IDLE (Idle line detected) pending bits are
* cleared by software sequence: a read operation to USART_SR register
* (USART_GetITStatus()) followed by a read operation to USART_DR
* register (USART_ReceiveData8() or USART_ReceiveData9()).
* @note RXNE pending bit can be also cleared by a read to the USART_DR register
* (USART_ReceiveData8() or USART_ReceiveData9()).
* @note TC (Transmit complete) pending bit can be also cleared by software
* sequence: a read operation to USART_SR register (USART_GetITStatus())
* followed by a write operation to USART_DR register (USART_SendData8()
* or USART_SendData9()).
* @note TXE pending bit is cleared only by a write to the USART_DR register
* (USART_SendData8() or USART_SendData9()).
* @retval None
*/
void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
{
uint8_t bitpos = 0x00, itmask = 0x00;
assert_param(IS_USART_CLEAR_IT(USART_IT));
bitpos = (uint8_t)( (uint8_t)((uint8_t)USART_IT & (uint8_t)0xF0) >> 0x04);
itmask = (uint8_t)( (uint8_t)0x01 << bitpos);
/*< Clear RXNE or TC pending bit */
USARTx->SR = (uint8_t)~itmask;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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