stm8l15x_clk.c

STM8L的tim4定时器使用

/**
  ******************************************************************************
  * @file    stm8l15x_clk.c
  * @author  MCD Application Team
  * @version V1.5.0
  * @date    13-May-2011
  * @brief   This file provides firmware functions to manage the following 
  *          functionalities of the clock controler (CLK) peripheral:
  *           - Internal/external clocks, CSS and CCO configuration
  *           - System clocks configuration
  *           - Peripheral clocks configuration
  *           - CSS on LSE configuration 
  *           - Low power clock configuration  
  *           - Interrupts and flags management
  *
  *  @verbatim
  *               
  *          ===================================================================
  *                               CLK specific features
  *          ===================================================================
  *    
  *          After reset the device is running from Internal High Speed oscillator
  *          divided by 8 (HSI/8 = 2MHz) with all peripherals off.
  *           - The clock for all peripherals is switched off, except for the BootROM 
  *             clock used for bootloader, in which case, the software should be properly 
  *             written to switch off that clock after the bootloader execution.     
  *
  *          Once the device starts from reset, the user application has to:
  *           - Configure the clock source to be used to drive the System clock
  *             (if the application needs higher frequency/performance)
  *           - Configure the System clock frequency  
  *           - Enable the clock for the peripheral(s) to be used
  *           - Configure the clock source(s) for peripherals which clocks are not
  *             derived from the System clock (RTC/LCD, BEEP)
  *
  *  @endverbatim
  *    
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************  
  */

/* Includes ------------------------------------------------------------------*/

#include "stm8l15x_clk.h"

/** @addtogroup STM8L15x_StdPeriph_Driver
  * @{
  */

/** @defgroup CLK 
  * @brief CLK driver modules
  * @{
  */ 
/* Private typedef -----------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private Variables ---------------------------------------------------------*/
/* Private Constant ---------------------------------------------------------*/
CONST uint8_t SYSDivFactor[5] = {1, 2, 4, 8, 16}; /*!< Holds the different Master clock Divider factors */
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup CLK_Private_Functions
  * @{
  */ 

/** @defgroup CLK_Group1 Internal and external clocks, CSS and CCO configuration functions
 *  @brief   Internal and external clocks, CSS and CCO configuration functions 
 *
@verbatim   
 ===============================================================================
      Internal/external clocks, CSS and CCO configuration functions
 ===============================================================================  

  This section provides functions allowing to configure the internal/external clocks,
  CSS and CCO pins.
  
  1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly as System 
     clock source.

  2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
     and/or BEEP clock source.

  3. HSE (high-speed external), 1 to 16 MHz crystal oscillator used directly as 
     System clock source. Can be used also as RTC/LCD clock source.

  4. LSE (low-speed external), 32 KHz oscillator used as RTC/LCD and/or BEEP clock source.

  5. CSS (Clock security system), once enabled and if a HSE clock failure occurs 
     (HSE used as System clock source), the System clock is automatically switched
     to HSI and an interrupt is generated if enabled. 

  6. CCO (configurable clock output), used to output HSI, LSE, HSE, HSI, LSI
     clock (through a configurable prescaler) on PC4 pin.

@endverbatim
  * @{
  */

/**
  * @brief  Deinitializes the CLK peripheral registers to their default reset values.
  * @param  None
  * @retval None
  */
void CLK_DeInit(void)
{
  CLK->ICKCR = CLK_ICKCR_RESET_VALUE;
  CLK->ECKCR = CLK_ECKCR_RESET_VALUE;
  CLK->CRTCR = CLK_CRTCR_RESET_VALUE;
  CLK->CBEEPR = CLK_CBEEPR_RESET_VALUE;
  CLK->SWR  = CLK_SWR_RESET_VALUE;
  CLK->SWCR = CLK_SWCR_RESET_VALUE;
  CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
  CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
  CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
  CLK->PCKENR3 = CLK_PCKENR3_RESET_VALUE;
  CLK->CSSR  = CLK_CSSR_RESET_VALUE;
  CLK->CCOR = CLK_CCOR_RESET_VALUE;
  CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
  CLK->HSICALR = CLK_HSICALR_RESET_VALUE;
  CLK->HSIUNLCKR = CLK_HSIUNLCKR_RESET_VALUE;
  CLK->REGCSR = CLK_REGCSR_RESET_VALUE;
}

/**
  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
  * @note   The HSI is stopped by hardware when entering Halt and active Halt modes.
  *         It is used (enabled by hardware) as system clock source after startup
  *         from Reset, wakeup from Halt and active Halt mode when the FHWU bit is
  *         set in the ICKCR register, or in case of HSE failure used as system clock
  *         (if the Clock Security System CSS is enabled).             
  * @note   HSI can not be stopped if it is used as active CCO source, as active 
  *         RTC clock, if the safe oscillator (AUX) is enabled or as system clock source,
  *         In this case, you have to select another source of the system clock 
  *         then stop the HSI.
  * @note   After enabling the HSI, the application software should wait on HSIRDY
  *         flag to be set indicating that HSI clock is stable and can be used as
  *         system clock source.  
  * @param  NewState: new state of the HSI.
    *         This parameter can be: ENABLE or DISABLE.
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
  *         clock cycles.  
  * @retval None
  */
void CLK_HSICmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    /* Set HSION bit */
    CLK->ICKCR |= CLK_ICKCR_HSION;
  }
  else
  {
    /* Reset HSION bit */
    CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_HSION);
  }
}

/**
  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
  * @note   The calibration is used to compensate for the variations in voltage
  *         and temperature that influence the frequency of the internal HSI RC.  
  * @param  CLK_HSICalibrationValue : calibration trimming value.
  *         This parameter must be a number between [(HSICALR regiter value) -12]
  *         and [(HSICALR regiter value) + 8 ]  
  * @note   Once HSITRIMR register configured, its value is used instead of the HSICALR
  *         register values. 
  * @retval None
  */
void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue)
{
  /* two consecutive write access to HSIUNLCKR register to unlock HSITRIMR */
  CLK->HSIUNLCKR = 0xAC;
  CLK->HSIUNLCKR = 0x35;

  /* Store the new value */
  CLK->HSITRIMR = (uint8_t)CLK_HSICalibrationValue;
}

/**
  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
  * @note   After enabling the LSI, the application software should wait on 
  *         LSIRDY flag to be set indicating that LSI clock is stable and can
  *         be used to clock the IWDG and/or the RTC.
  * @note   LSI can not be disabled if used as system clock source, as active CCO 
  *         source, as BEEP clock source while BEEPAHALT bit is set or, as RTC active 
  *         clock source.     
  * @param  NewState: new state of the LSI.
  *          This parameter can be: ENABLE or DISABLE.
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
  *         clock cycles. 
  * @retval None
  */
void CLK_LSICmd(FunctionalState NewState)
{

  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    /* Set LSION bit */
    CLK->ICKCR |= CLK_ICKCR_LSION;
  }
  else
  {
    /* Reset LSION bit */
    CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_LSION);
  }
}

/**
  * @brief  Configures the External High Speed oscillator (HSE).
  * @note   After enabling the HSE (CLK_HSE_ON or CLK_HSE_Bypass), the application
  *         software should wait on HSERDY flag to be set indicating that HSE clock
  *         is stable and can be used to clock the system.
  * @note   HSE state can not be changed if it is used as system clock. In this case,
  *         you have to select another source of the system clock then change 
  *         the HSE state (ex. disable it).
  * @note   The HSE is stopped by hardware when entering HALT and active HALT modes.  
  * @param  CLK_HSE: specifies the new state of the HSE.
  *         This parameter can be one of the following values:
  *            @arg CLK_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
  *                              6 HSE oscillator clock cycles.
  *            @arg CLK_HSE_ON: turn ON the HSE oscillator
  *            @arg CLK_HSE_Bypass: HSE oscillator bypassed with external clock
  * @note   In case of Enabling HSE Bypass make sure that the HSE clock source is
  *         not used by the RTC, output or involved in a switching operation.
  * @retval None
  */
void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE)
{
  /* Check the parameters */
  assert_param(IS_CLK_HSE(CLK_HSE));

  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
  /* Reset HSEON bit */
  CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEON;

  /* Reset HSEBYP bit */
  CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEBYP;

  /* Configure HSE */
  CLK->ECKCR |= (uint8_t)CLK_HSE;
}

/**
  * @brief  Configures the External Low Speed oscillator (LSE).
  * @note   After enabling the LSE (CLK_LSE_ON or CLK_LSE_Bypass), the application
  *         software should wait on LSERDY flag to be set indicating that LSE clock
  *         is stable and can be used to clock the RTC.
  * @param  CLK_LSE: specifies the new state of the LSE.
  *         This parameter can be one of the following values:
  *            @arg CLK_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
  *                              6 LSE oscillator clock cycles.
  *            @arg CLK_LSE_ON: turn ON the LSE oscillator
  *            @arg CLK_LSE_Bypass: LSE oscillator bypassed with external clock
  * @note   In case of Enabling LSE Bypass make sure that the LSE clock source is
  *         not used by the RTC, output or involved in a switching operation.  
  * @retval None
  */
void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE)
{
  /* Check the parameters */
  assert_param(IS_CLK_LSE(CLK_LSE));

  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
  /* Reset LSEON bit */
  CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEON;

  /* Reset LSEBYP bit */
  CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEBYP;

  /* Configure LSE */
  CLK->ECKCR |= (uint8_t)CLK_LSE;

}

/**
  * @brief  Enables the Clock Security System.
  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
  *         is automatically disabled and an interrupt is generated to inform the
  *         software about the failure allowing the MCU to perform rescue operations.
  * @note   Once CSS is enabled it cannot be disabled until the next reset.  
  * @param  None
  * @retval None
  */
void CLK_ClockSecuritySystemEnable(void)
{
  /* Set CSSEN bit */
  CLK->CSSR |= CLK_CSSR_CSSEN;
}

/**
  * @brief  Enables the Clock Security System deglitcher system.
  * @param  None
  * @retval None
  */
void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    /* Set CSSDGON bit */
    CLK->CSSR |= CLK_CSSR_CSSDGON;
  }
  else
  {
    /* Reset CSSDGON  bit */
    CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDGON);
  }
}

/**
  * @brief  Selects the clock source to output on CCO pin(PC4).
  * @note   PC4 should be configured output push-pull with the speed that matches 
  *         maximum output speed of the desired clock.
  * @param  CLK_CCOSource: specifies the clock source to output.
  *          This parameter can be one of the following values:
  *            @arg CLK_CCOSource_Off: No clock selected as CCO source
  *            @arg CLK_CCOSource_HSI: HSI clock selected as CCO source
  *            @arg CLK_CCOSource_LSI: LSI clock selected as CCO source
  *            @arg CLK_CCOSource_LSE: LSE clock selected as CCO source
  *            @arg CLK_CCOSource_HSE: HSE clock selected as CCO source
  * @param  CLK_CCODiv: specifies the CCO prescaler.
  *          This parameter can be one of the following values:
  *            @arg CLK_CCODiv_1: no division applied to CCO clock
  *            @arg CLK_CCODiv_2: division by 2 applied to CCO clock
  *            @arg CLK_CCODiv_4: division by 4 applied to CCO clock
  *            @arg CLK_CCODiv_8: division by 8 applied to CCO clock
  *            @arg CLK_CCODiv_16: division by 16 applied to CCO clock
  *            @arg CLK_CCODiv_32: division by 32 applied to CCO clock
  *            @arg CLK_CCODiv_64: division by 64 applied to CCO clock
  * @retval None
  */
void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv)
{
  /* check teh parameters */
  assert_param(IS_CLK_OUTPUT(CLK_CCOSource));
  assert_param(IS_CLK_OUTPUT_DIVIDER(CLK_CCODiv));

  /* Selects the source provided on cco_ck output and its divider*/
  CLK->CCOR = (uint8_t)((uint8_t)CLK_CCOSource | (uint8_t)CLK_CCODiv);
}

/**
  * @}
  */

/** @defgroup CLK_Group2 System clock configuration functions
 *  @brief   System clock configuration functions
 *
@verbatim   
 ===============================================================================
                    System clock configuration functions
 ===============================================================================  

  This section provides functions allowing to configure the System clock.