📄 stm8l15x_dac.c
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/**
******************************************************************************
* @file stm8l15x_dac.c
* @author MCD Application Team
* @version V1.5.0
* @date 13-May-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* - DAC channels configuration: trigger, output buffer, data format
* - DMA management
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* DAC Peripheral features
* ===================================================================
* The device integrates two 12-bit Digital Analog Converters that can
* be used independently or simultaneously (dual mode):
* 1- DAC channel1 with DAC_OUT1 (PF0) as output
* 1- DAC channel2 with DAC_OUT2 (PF1) as output
*
* Digital to Analog conversion can be non-triggered using DAC_Trigger_None
* and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
* DAC_SetChannel1Data()/DAC_SetChannel2Data.
*
* Digital to Analog conversion can be triggered by:
* 1- External event: PE4 using DAC_Trigger_Ext.
* This pin (PE4) must be configured in input mode.
*
* 2- Timers TRGO: TIM4, TIM5
* (DAC_Trigger_T4_TRGO, DAC_Trigger_T5_TRGO)
* The timer TRGO event should be selected using TIMx_SelectOutputTrigger()
*
* 3- Software using DAC_Trigger_Software
*
* Each DAC channel integrates an output buffer that can be used to
* reduce the output impedance, and to drive external loads directly
* without having to add an external operational amplifier.
*
* Refer to the device datasheet for more details about output impedance
* value with and without output buffer.
*
* Both DAC channels can be used to generate
* 1- Noise wave using DAC_Wave_Noise
* 2- Triangle wave using DAC_Wave_Triangle
*
*
* The DAC data format can be:
* 1- 8-bit right alignment using DAC_Align_8b_R
* 2- 12-bit left alignment using DAC_Align_12b_L
* 3- 12-bit right alignment using DAC_Align_12b_R
*
* The analog output voltage on each DAC channel pin is determined
* by the following equation: DAC_OUTx = VREF+ * DOR / 4095
* with DOR is the Data Output Register
* VEF+ is the input voltage reference (refer to the device datasheet)
* e.g. To set DAC_OUT1 to 0.7V, use
* DAC_SetChannel1Data(DAC_Align_12b_R, 868);
* Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
*
* A DMA1 request can be generated when an external trigger (but not
* a software trigger) occurs if DMA1 requests are enabled using
* DAC_DMACmd()
* DMA1 requests are mapped as following:
* 1- DAC channel1 is mapped on DMA1 channel3 which must be already
* configured
* 2- DAC channel2 is mapped on DMA1 channel1 which must be already
* configured
*
* ===================================================================
* How to use this driver
* ===================================================================
* - DAC clock must be enabled to get write access to DAC registers using
* CLK_PeripheralClockConfig(CLK_Peripheral_DAC, ENABLE)
* - Configure DAC_OUTx (DAC_OUT1: PF0, DAC_OUT2: PF1) in analog mode.
* - Configure the DAC channel using DAC_Init()
* - Enable the DAC channel using DAC_Cmd()
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_dac.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DAC_Private_Functions
* @{
*/
/** @defgroup DAC_Group1 DAC channels configuration
* @brief DAC channels configuration: trigger, output buffer, data format
*
@verbatim
===============================================================================
DAC channels configuration: trigger, output buffer, data format
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void DAC_DeInit(void)
{
/* Set Channel1 the Configuration registers to their reset values */
DAC->CH1CR1 = DAC_CR1_RESET_VALUE;
DAC->CH1CR2 = DAC_CR2_RESET_VALUE;
/* Set Channel2 the Configuration registers to their reset values */
DAC->CH2CR1 = DAC_CR1_RESET_VALUE;
DAC->CH2CR2 = DAC_CR2_RESET_VALUE;
/* Set the Software Trigger configuration registers to their reset values */
DAC->SWTRIGR = DAC_SWTRIGR_RESET_VALUE;
/* Set the Status registers to their reset values */
DAC->SR = (uint8_t)~DAC_SR_RESET_VALUE;
/* Set the Channel1 Data holding registers to their reset values */
DAC->CH1RDHRH = DAC_RDHRH_RESET_VALUE;
DAC->CH1RDHRL = DAC_RDHRL_RESET_VALUE;
DAC->CH1LDHRH = DAC_LDHRH_RESET_VALUE;
DAC->CH1LDHRL = DAC_LDHRL_RESET_VALUE;
DAC->CH1DHR8 = DAC_DHR8_RESET_VALUE;
/* Set the Channel2 Data holding registers to their reset values */
DAC->CH2RDHRH = DAC_RDHRH_RESET_VALUE;
DAC->CH2RDHRL = DAC_RDHRL_RESET_VALUE;
DAC->CH2LDHRH = DAC_LDHRH_RESET_VALUE;
DAC->CH2LDHRL = DAC_LDHRL_RESET_VALUE;
DAC->CH2DHR8 = DAC_DHR8_RESET_VALUE;
/* Set the Dual mode 12bit Right Data holding registers to their reset values */
DAC->DCH1RDHRH = DAC_RDHRH_RESET_VALUE;
DAC->DCH1RDHRL = DAC_RDHRL_RESET_VALUE;
DAC->DCH2RDHRH = DAC_RDHRH_RESET_VALUE;
DAC->DCH2RDHRL = DAC_RDHRL_RESET_VALUE;
/* Set the Dual mode 12bit Left Data holding registers to their reset values */
DAC->DCH1LDHRH = DAC_LDHRH_RESET_VALUE;
DAC->DCH1LDHRL = DAC_LDHRL_RESET_VALUE;
DAC->DCH2LDHRH = DAC_LDHRH_RESET_VALUE;
DAC->DCH2LDHRL = DAC_LDHRL_RESET_VALUE;
/* Set the Dual mode 8bit Data holding registers to their reset values */
DAC->DCH1DHR8 = DAC_DHR8_RESET_VALUE;
DAC->DCH2DHR8 = DAC_DHR8_RESET_VALUE;
}
/**
* @brief Initializes the DAC according to the specified parameters.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Trigger : the selected DAC trigger.
* This parameter can be one of the following values:
* @arg DAC_Trigger_None: DAC trigger None
* @arg DAC_Trigger_T4_TRGO: DAC trigger TIM4 TRGO
* @arg DAC_Trigger_T5_TRGO: DAC trigger TIM5 TRGO
* @arg DAC_Trigger_Ext: DAC trigger External Trigger (PE4)
* @arg DAC_Trigger_Software: DAC trigger software
* @param DAC_OutputBuffer : the status of DAC load Buffer
* This parameter can be one of the following values:
* @arg DAC_OutputBuffer_Enable: DAC output buffer Enabled
* @arg DAC_OutputBuffer_Disable: DAC output buffer Disabled
* @retval None
*/
void DAC_Init(DAC_Channel_TypeDef DAC_Channel,
DAC_Trigger_TypeDef DAC_Trigger,
DAC_OutputBuffer_TypeDef DAC_OutputBuffer)
{
uint8_t tmpreg = 0;
uint16_t tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_TRIGGER(DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_OutputBuffer));
/* Get the DAC CHxCR1 value */
tmpreg2 = (uint16_t)((uint8_t)((uint8_t)DAC_Channel << 1));
tmpreg = *(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2));
/* Clear BOFFx, TENx, TSELx bits */
tmpreg &= (uint8_t)~(DAC_CR1_BOFF | DAC_CR1_TEN | DAC_CR1_TSEL );
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg |= (uint8_t)(DAC_OutputBuffer);
/* Configure for the selected DAC channel trigger*/
if (DAC_Trigger != DAC_Trigger_None)
{
/* Set TSELx and TEN bits according to DAC_Trigger value */
tmpreg |= (uint8_t)(DAC_CR1_TEN | DAC_Trigger) ;
}
/* Write to DAC CHxCR1 */
*(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2)) = (uint8_t)tmpreg;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @note When the DAC channel is enabled the trigger source can no more
* be modified.
* @retval None
*/
void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
{
uint16_t cr1addr = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Find CHxCR1 register Address */
cr1addr = DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
(*(uint8_t*)(cr1addr)) |= DAC_CR1_EN;
}
else
{
/* Disable the selected DAC channel */
(*(uint8_t*)(cr1addr)) &= (uint8_t) ~(DAC_CR1_EN);
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
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