stm8l15x_clk.h

STM8L的tim4定时器使用

/**
  ******************************************************************************
  * @file    stm8l15x_clk.h
  * @author  MCD Application Team
  * @version V1.5.0
  * @date    13-May-2011
  * @brief   This file contains all the functions prototypes for the CLK firmware
  *          library.
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************  
  */


/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_CLK_H
#define __STM8L15x_CLK_H

/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"

/** @addtogroup STM8L15x_StdPeriph_Driver
  * @{
  */

/** @addtogroup CLK
  * @{
  */ 
/* Exported types ------------------------------------------------------------*/

/** @defgroup Exported_Types
  * @{
  */
  
/** @defgroup CLK_HSE_Configuration
  * @{
  */
typedef enum {
  CLK_HSE_OFF    = (uint8_t)0x00, /*!< HSE Diasble */
  CLK_HSE_ON     = (uint8_t)0x01, /*!< HSE Enable */
  CLK_HSE_Bypass = (uint8_t)0x11  /*!< HSE Bypass and enable */
} CLK_HSE_TypeDef;

#define IS_CLK_HSE(CONFIG) (((CONFIG) == CLK_HSE_ON) ||\
                            ((CONFIG) == CLK_HSE_OFF)||\
                            ((CONFIG) == CLK_HSE_Bypass))
/**
  * @}
  */
                              
/** @defgroup CLK_LSE_Configuration
  * @{
  */
typedef enum {
  CLK_LSE_OFF    = (uint8_t)0x00, /*!< LSE Diasble */
  CLK_LSE_ON     = (uint8_t)0x04, /*!< LSE Enable */
  CLK_LSE_Bypass = (uint8_t)0x24  /*!< LSE Bypass and enable */
} CLK_LSE_TypeDef;

#define IS_CLK_LSE(CONFIG) (((CONFIG) == CLK_LSE_OFF) ||\
                            ((CONFIG) == CLK_LSE_ON)  ||\
                            ((CONFIG) == CLK_LSE_Bypass))
/**
  * @}
  */

/** @defgroup CLK_System_Clock_Sources
  * @{
  */
typedef enum {
  CLK_SYSCLKSource_HSI = (uint8_t)0x01, /*!< System Clock Source HSI */
  CLK_SYSCLKSource_LSI = (uint8_t)0x02, /*!< System Clock Source LSI */
  CLK_SYSCLKSource_HSE = (uint8_t)0x04, /*!< System Clock Source HSE */
  CLK_SYSCLKSource_LSE = (uint8_t)0x08  /*!< System Clock Source LSE */
} CLK_SYSCLKSource_TypeDef;

#define IS_CLK_SOURCE(SOURCE) (((SOURCE) == CLK_SYSCLKSource_HSI) ||\
                               ((SOURCE) == CLK_SYSCLKSource_LSI) ||\
                               ((SOURCE) == CLK_SYSCLKSource_HSE) ||\
                               ((SOURCE) == CLK_SYSCLKSource_LSE))
/**
  * @}
  */

/** @defgroup CLK_Clock_Output_Selection
  * @{
  */
typedef enum {
  CLK_CCOSource_Off = (uint8_t)0x00, /*!< Clock Output Off */
  CLK_CCOSource_HSI = (uint8_t)0x02, /*!< HSI Clock Output  */
  CLK_CCOSource_LSI = (uint8_t)0x04, /*!< LSI Clock Output */
  CLK_CCOSource_HSE = (uint8_t)0x08, /*!< HSE Clock Output */
  CLK_CCOSource_LSE = (uint8_t)0x10  /*!< LSE Clock Output */
} CLK_CCOSource_TypeDef;

#define IS_CLK_OUTPUT(OUTPUT)  (((OUTPUT) == CLK_CCOSource_Off)  ||\
                                ((OUTPUT) == CLK_CCOSource_HSI)  ||\
                                ((OUTPUT) == CLK_CCOSource_LSI)  ||\
                                ((OUTPUT) == CLK_CCOSource_HSE)  ||\
                                ((OUTPUT) == CLK_CCOSource_LSE))
/**
  * @}
  */
     
/** @defgroup CLK_Clock_Output_Prescaler
  * @{
  */
typedef enum {
  CLK_CCODiv_1  = (uint8_t)0x00, /*!< Clock Output Div 1 */
  CLK_CCODiv_2  = (uint8_t)0x20, /*!< Clock Output Div 2 */
  CLK_CCODiv_4  = (uint8_t)0x40, /*!< Clock Output Div 4 */
  CLK_CCODiv_8  = (uint8_t)0x60, /*!< Clock Output Div 8 */
  CLK_CCODiv_16 = (uint8_t)0x80, /*!< Clock Output Div 16 */
  CLK_CCODiv_32 = (uint8_t)0xA0, /*!< Clock Output Div 32 */
  CLK_CCODiv_64 = (uint8_t)0xC0  /*!< Clock Output Div 64 */
} CLK_CCODiv_TypeDef;

#define IS_CLK_OUTPUT_DIVIDER(PRESCALER) (((PRESCALER) == CLK_CCODiv_1)  ||\
                                          ((PRESCALER) == CLK_CCODiv_2)  ||\
                                          ((PRESCALER) == CLK_CCODiv_4)  ||\
                                          ((PRESCALER) == CLK_CCODiv_8)  ||\
                                          ((PRESCALER) == CLK_CCODiv_16) ||\
                                          ((PRESCALER) == CLK_CCODiv_32) ||\
                                          ((PRESCALER) == CLK_CCODiv_64))
/**
  * @}
  */
  
/** @defgroup CLK_Beep_Selection
  * @{
  */
typedef enum {
  CLK_BEEPCLKSource_Off = (uint8_t)0x00, /*!< Clock BEEP Off */
  CLK_BEEPCLKSource_LSI = (uint8_t)0x02, /*!< Clock BEEP : LSI */
  CLK_BEEPCLKSource_LSE = (uint8_t)0x04  /*!< Clock BEEP : LSE */
} CLK_BEEPCLKSource_TypeDef;

#define IS_CLK_CLOCK_BEEP(OUTPUT) (((OUTPUT) == CLK_BEEPCLKSource_Off)  ||\
                                   ((OUTPUT) == CLK_BEEPCLKSource_LSI)  ||\
                                   ((OUTPUT) == CLK_BEEPCLKSource_LSE))
/**
  * @}
  */
  
/** @defgroup CLK_RTC_Selection
  * @{
  */
typedef enum {
  CLK_RTCCLKSource_Off = (uint8_t)0x00, /*!< Clock RTC Off */
  CLK_RTCCLKSource_HSI = (uint8_t)0x02, /*!< Clock RTC : HSI */
  CLK_RTCCLKSource_LSI = (uint8_t)0x04, /*!< Clock RTC : LSI */
  CLK_RTCCLKSource_HSE = (uint8_t)0x08, /*!< Clock RTC : HSE */
  CLK_RTCCLKSource_LSE = (uint8_t)0x10  /*!< Clock RTC : LSE */
} CLK_RTCCLKSource_TypeDef;

#define IS_CLK_CLOCK_RTC(OUTPUT) (((OUTPUT) == CLK_RTCCLKSource_Off)  ||\
                                  ((OUTPUT) == CLK_RTCCLKSource_HSI)  ||\
                                  ((OUTPUT) == CLK_RTCCLKSource_LSI)  ||\
                                  ((OUTPUT) == CLK_RTCCLKSource_HSE)  ||\
                                  ((OUTPUT) == CLK_RTCCLKSource_LSE))
/**
  * @}
  */
  
/** @defgroup CLK_RTC_Prescaler
  * @{
  */
typedef enum {
  CLK_RTCCLKDiv_1  = (uint8_t)0x00, /*!< Clock RTC Div 1 */
  CLK_RTCCLKDiv_2  = (uint8_t)0x20, /*!< Clock RTC Div 2  */
  CLK_RTCCLKDiv_4  = (uint8_t)0x40, /*!< Clock RTC Div 4 */
  CLK_RTCCLKDiv_8  = (uint8_t)0x60, /*!< Clock RTC Div 8 */
  CLK_RTCCLKDiv_16 = (uint8_t)0x80, /*!< Clock RTC Div 16 */
  CLK_RTCCLKDiv_32 = (uint8_t)0xA0, /*!< Clock RTC  Div 32 */
  CLK_RTCCLKDiv_64 = (uint8_t)0xC0  /*!< Clock RTC  Div 64 */
} CLK_RTCCLKDiv_TypeDef;

#define IS_CLK_CLOCK_RTC_DIV(DIV) (((DIV) == CLK_RTCCLKDiv_1)  ||\
                                   ((DIV) == CLK_RTCCLKDiv_2)  ||\
                                   ((DIV) == CLK_RTCCLKDiv_4)  ||\
                                   ((DIV) == CLK_RTCCLKDiv_8)  ||\
                                   ((DIV) == CLK_RTCCLKDiv_16) ||\
                                   ((DIV) == CLK_RTCCLKDiv_32) ||\
                                   ((DIV) == CLK_RTCCLKDiv_64))
/**
  * @}
  */
  
/** @defgroup CLK_Peripherals
  * @{
  */
/* Elements values convention: 0xXY
        X = choice between the peripheral registers
        X = 0 : PCKENR1
        X = 1 : PCKENR2
        X = 2 : PCKENR3
        Y = Peripheral position in the register
  */        
typedef enum {
  CLK_Peripheral_TIM2    = (uint8_t)0x00, /*!< Peripheral Clock Enable 1, TIM2 */
  CLK_Peripheral_TIM3    = (uint8_t)0x01, /*!< Peripheral Clock Enable 1, TIM3 */
  CLK_Peripheral_TIM4    = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, TIM4 */
  CLK_Peripheral_I2C1    = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, I2C1 */
  CLK_Peripheral_SPI1    = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, SPI1 */
  CLK_Peripheral_USART1  = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, USART1 */
  CLK_Peripheral_BEEP    = (uint8_t)0x06, /*!< Peripheral Clock Enable 1, BEEP */
  CLK_Peripheral_DAC     = (uint8_t)0x07, /*!< Peripheral Clock Enable 1, DAC */
  CLK_Peripheral_ADC1    = (uint8_t)0x10, /*!< Peripheral Clock Enable 2, ADC1 */
  CLK_Peripheral_TIM1    = (uint8_t)0x11, /*!< Peripheral Clock Enable 2, TIM1 */
  CLK_Peripheral_RTC     = (uint8_t)0x12, /*!< Peripheral Clock Enable 2, RTC */
  CLK_Peripheral_LCD     = (uint8_t)0x13, /*!< Peripheral Clock Enable 2, LCD */