📄 stm8l15x_tim4.ls
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1182 ; 470 FlagStatus bitstatus = RESET;
1184 ; 473 assert_param(IS_TIM4_GET_FLAG(TIM4_FLAG));
1186 ; 475 if ((TIM4->SR1 & (uint8_t)TIM4_FLAG) != 0)
1188 00c2 c452e5 and a,21221
1189 00c5 2706 jreq L735
1190 ; 477 bitstatus = SET;
1192 00c7 a601 ld a,#1
1193 00c9 6b01 ld (OFST+0,sp),a
1195 00cb 2002 jra L145
1196 00cd L735:
1197 ; 481 bitstatus = RESET;
1199 00cd 0f01 clr (OFST+0,sp)
1200 00cf L145:
1201 ; 483 return ((FlagStatus)bitstatus);
1203 00cf 7b01 ld a,(OFST+0,sp)
1206 00d1 5b01 addw sp,#1
1207 00d3 81 ret
1242 ; 494 void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG)
1242 ; 495 {
1243 switch .text
1244 00d4 _TIM4_ClearFlag:
1248 ; 497 assert_param(IS_TIM4_CLEAR_FLAG((uint8_t)TIM4_FLAG));
1250 ; 499 TIM4->SR1 = (uint8_t)(~((uint8_t)TIM4_FLAG));
1252 00d4 43 cpl a
1253 00d5 c752e5 ld 21221,a
1254 ; 500 }
1257 00d8 81 ret
1321 ; 512 ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT)
1321 ; 513 {
1322 switch .text
1323 00d9 _TIM4_GetITStatus:
1325 00d9 88 push a
1326 00da 89 pushw x
1327 00000002 OFST: set 2
1330 ; 514 ITStatus bitstatus = RESET;
1332 ; 516 uint8_t itStatus = 0x0, itEnable = 0x0;
1336 ; 519 assert_param(IS_TIM4_GET_IT(TIM4_IT));
1338 ; 521 itStatus = (uint8_t)(TIM4->SR1 & (uint8_t)TIM4_IT);
1340 00db c452e5 and a,21221
1341 00de 6b01 ld (OFST-1,sp),a
1342 ; 523 itEnable = (uint8_t)(TIM4->IER & (uint8_t)TIM4_IT);
1344 00e0 c652e4 ld a,21220
1345 00e3 1403 and a,(OFST+1,sp)
1346 00e5 6b02 ld (OFST+0,sp),a
1347 ; 525 if ((itStatus != (uint8_t)RESET ) && (itEnable != (uint8_t)RESET ))
1349 00e7 0d01 tnz (OFST-1,sp)
1350 00e9 270a jreq L316
1352 00eb 0d02 tnz (OFST+0,sp)
1353 00ed 2706 jreq L316
1354 ; 527 bitstatus = (ITStatus)SET;
1356 00ef a601 ld a,#1
1357 00f1 6b02 ld (OFST+0,sp),a
1359 00f3 2002 jra L516
1360 00f5 L316:
1361 ; 531 bitstatus = (ITStatus)RESET;
1363 00f5 0f02 clr (OFST+0,sp)
1364 00f7 L516:
1365 ; 533 return ((ITStatus)bitstatus);
1367 00f7 7b02 ld a,(OFST+0,sp)
1370 00f9 5b03 addw sp,#3
1371 00fb 81 ret
1407 ; 544 void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT)
1407 ; 545 {
1408 switch .text
1409 00fc _TIM4_ClearITPendingBit:
1413 ; 547 assert_param(IS_TIM4_IT(TIM4_IT));
1415 ; 550 TIM4->SR1 = (uint8_t)(~(uint8_t)TIM4_IT);
1417 00fc 43 cpl a
1418 00fd c752e5 ld 21221,a
1419 ; 551 }
1422 0100 81 ret
1481 ; 562 void TIM4_DMACmd( TIM4_DMASource_TypeDef TIM4_DMASource, FunctionalState NewState)
1481 ; 563 {
1482 switch .text
1483 0101 _TIM4_DMACmd:
1485 0101 89 pushw x
1486 00000000 OFST: set 0
1489 ; 565 assert_param(IS_FUNCTIONAL_STATE(NewState));
1491 ; 566 assert_param(IS_TIM4_DMA_SOURCE(TIM4_DMASource));
1493 ; 568 if (NewState != DISABLE)
1495 0102 9f ld a,xl
1496 0103 4d tnz a
1497 0104 2709 jreq L566
1498 ; 571 TIM4->DER |= (uint8_t)TIM4_DMASource;
1500 0106 9e ld a,xh
1501 0107 ca52e3 or a,21219
1502 010a c752e3 ld 21219,a
1504 010d 2009 jra L766
1505 010f L566:
1506 ; 576 TIM4->DER &= (uint8_t)~TIM4_DMASource;
1508 010f 7b01 ld a,(OFST+1,sp)
1509 0111 43 cpl a
1510 0112 c452e3 and a,21219
1511 0115 c752e3 ld 21219,a
1512 0118 L766:
1513 ; 578 }
1516 0118 85 popw x
1517 0119 81 ret
1541 ; 601 void TIM4_InternalClockConfig(void)
1541 ; 602 {
1542 switch .text
1543 011a _TIM4_InternalClockConfig:
1547 ; 604 TIM4->SMCR &= (uint8_t)(~TIM4_SMCR_SMS);
1549 011a c652e2 ld a,21218
1550 011d a4f8 and a,#248
1551 011f c752e2 ld 21218,a
1552 ; 605 }
1555 0122 81 ret
1639 ; 645 void TIM4_SelectInputTrigger(TIM4_TRGSelection_TypeDef TIM4_InputTriggerSource)
1639 ; 646 {
1640 switch .text
1641 0123 _TIM4_SelectInputTrigger:
1643 0123 88 push a
1644 0124 88 push a
1645 00000001 OFST: set 1
1648 ; 647 uint8_t tmpsmcr = 0;
1650 ; 650 assert_param(IS_TIM4_TRIGGER_SELECTION(TIM4_InputTriggerSource));
1652 ; 652 tmpsmcr = TIM4->SMCR;
1654 0125 c652e2 ld a,21218
1655 0128 6b01 ld (OFST+0,sp),a
1656 ; 655 tmpsmcr &= (uint8_t)(~TIM4_SMCR_TS);
1658 012a 7b01 ld a,(OFST+0,sp)
1659 012c a48f and a,#143
1660 012e 6b01 ld (OFST+0,sp),a
1661 ; 656 tmpsmcr |= (uint8_t)TIM4_InputTriggerSource;
1663 0130 7b01 ld a,(OFST+0,sp)
1664 0132 1a02 or a,(OFST+1,sp)
1665 0134 6b01 ld (OFST+0,sp),a
1666 ; 658 TIM4->SMCR = (uint8_t)tmpsmcr;
1668 0136 7b01 ld a,(OFST+0,sp)
1669 0138 c752e2 ld 21218,a
1670 ; 659 }
1673 013b 85 popw x
1674 013c 81 ret
1749 ; 670 void TIM4_SelectOutputTrigger(TIM4_TRGOSource_TypeDef TIM4_TRGOSource)
1749 ; 671 {
1750 switch .text
1751 013d _TIM4_SelectOutputTrigger:
1753 013d 88 push a
1754 013e 88 push a
1755 00000001 OFST: set 1
1758 ; 672 uint8_t tmpcr2 = 0;
1760 ; 675 assert_param(IS_TIM4_TRGO_SOURCE(TIM4_TRGOSource));
1762 ; 677 tmpcr2 = TIM4->CR2;
1764 013f c652e1 ld a,21217
1765 0142 6b01 ld (OFST+0,sp),a
1766 ; 680 tmpcr2 &= (uint8_t)(~TIM4_CR2_MMS);
1768 0144 7b01 ld a,(OFST+0,sp)
1769 0146 a48f and a,#143
1770 0148 6b01 ld (OFST+0,sp),a
1771 ; 683 tmpcr2 |= (uint8_t)TIM4_TRGOSource;
1773 014a 7b01 ld a,(OFST+0,sp)
1774 014c 1a02 or a,(OFST+1,sp)
1775 014e 6b01 ld (OFST+0,sp),a
1776 ; 685 TIM4->CR2 = tmpcr2;
1778 0150 7b01 ld a,(OFST+0,sp)
1779 0152 c752e1 ld 21217,a
1780 ; 686 }
1783 0155 85 popw x
1784 0156 81 ret
1875 ; 700 void TIM4_SelectSlaveMode(TIM4_SlaveMode_TypeDef TIM4_SlaveMode)
1875 ; 701 {
1876 switch .text
1877 0157 _TIM4_SelectSlaveMode:
1879 0157 88 push a
1880 0158 88 push a
1881 00000001 OFST: set 1
1884 ; 702 uint8_t tmpsmcr = 0;
1886 ; 705 assert_param(IS_TIM4_SLAVE_MODE(TIM4_SlaveMode));
1888 ; 707 tmpsmcr = TIM4->SMCR;
1890 0159 c652e2 ld a,21218
1891 015c 6b01 ld (OFST+0,sp),a
1892 ; 710 tmpsmcr &= (uint8_t)(~TIM4_SMCR_SMS);
1894 015e 7b01 ld a,(OFST+0,sp)
1895 0160 a4f8 and a,#248
1896 0162 6b01 ld (OFST+0,sp),a
1897 ; 713 tmpsmcr |= (uint8_t)TIM4_SlaveMode;
1899 0164 7b01 ld a,(OFST+0,sp)
1900 0166 1a02 or a,(OFST+1,sp)
1901 0168 6b01 ld (OFST+0,sp),a
1902 ; 715 TIM4->SMCR = tmpsmcr;
1904 016a 7b01 ld a,(OFST+0,sp)
1905 016c c752e2 ld 21218,a
1906 ; 716 }
1909 016f 85 popw x
1910 0170 81 ret
1946 ; 724 void TIM4_SelectMasterSlaveMode(FunctionalState NewState)
1946 ; 725 {
1947 switch .text
1948 0171 _TIM4_SelectMasterSlaveMode:
1952 ; 727 assert_param(IS_FUNCTIONAL_STATE(NewState));
1954 ; 730 if (NewState != DISABLE)
1956 0171 4d tnz a
1957 0172 2706 jreq L1501
1958 ; 732 TIM4->SMCR |= TIM4_SMCR_MSM;
1960 0174 721e52e2 bset 21218,#7
1962 0178 2004 jra L3501
1963 017a L1501:
1964 ; 736 TIM4->SMCR &= (uint8_t)(~TIM4_SMCR_MSM);
1966 017a 721f52e2 bres 21218,#7
1967 017e L3501:
1968 ; 738 }
1971 017e 81 ret
1984 xdef _TIM4_SelectMasterSlaveMode
1985 xdef _TIM4_SelectSlaveMode
1986 xdef _TIM4_SelectOutputTrigger
1987 xdef _TIM4_SelectInputTrigger
1988 xdef _TIM4_InternalClockConfig
1989 xdef _TIM4_DMACmd
1990 xdef _TIM4_ClearITPendingBit
1991 xdef _TIM4_GetITStatus
1992 xdef _TIM4_ClearFlag
1993 xdef _TIM4_GetFlagStatus
1994 xdef _TIM4_GenerateEvent
1995 xdef _TIM4_ITConfig
1996 xdef _TIM4_Cmd
1997 xdef _TIM4_SelectOnePulseMode
1998 xdef _TIM4_ARRPreloadConfig
1999 xdef _TIM4_UpdateRequestConfig
2000 xdef _TIM4_UpdateDisableConfig
2001 xdef _TIM4_GetPrescaler
2002 xdef _TIM4_GetCounter
2003 xdef _TIM4_SetAutoreload
2004 xdef _TIM4_SetCounter
2005 xdef _TIM4_PrescalerConfig
2006 xdef _TIM4_TimeBaseInit
2007 xdef _TIM4_DeInit
2026 end
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