📄 stm8l15x_clk.ls
字号:
2193 0247 2022 jra L1211
2194 0249 L5111:
2195 ; 891 CLK->CSSR |= CLK_CSSR_CSSDIE;
2197 0249 721450ca bset 20682,#2
2198 024d 201c jra L1211
2199 024f L7011:
2200 ; 896 if (CLK_IT == CLK_IT_SWIF)
2202 024f 7b01 ld a,(OFST+1,sp)
2203 0251 a11c cp a,#28
2204 0253 2606 jrne L3211
2205 ; 899 CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
2207 0255 721550c9 bres 20681,#2
2209 0259 2010 jra L1211
2210 025b L3211:
2211 ; 901 else if (CLK_IT == CLK_IT_LSECSSF)
2213 025b 7b01 ld a,(OFST+1,sp)
2214 025d a12c cp a,#44
2215 025f 2606 jrne L7211
2216 ; 904 CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSIE);
2218 0261 72155190 bres 20880,#2
2220 0265 2004 jra L1211
2221 0267 L7211:
2222 ; 909 CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);
2224 0267 721550ca bres 20682,#2
2225 026b L1211:
2226 ; 912 }
2229 026b 85 popw x
2230 026c 81 ret
2453 ; 939 FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG)
2453 ; 940 {
2454 switch .text
2455 026d _CLK_GetFlagStatus:
2457 026d 88 push a
2458 026e 89 pushw x
2459 00000002 OFST: set 2
2462 ; 941 uint8_t reg = 0;
2464 ; 942 uint8_t pos = 0;
2466 ; 943 FlagStatus bitstatus = RESET;
2468 ; 946 assert_param(IS_CLK_FLAGS(CLK_FLAG));
2470 ; 949 reg = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0xF0);
2472 026f a4f0 and a,#240
2473 0271 6b02 ld (OFST+0,sp),a
2474 ; 952 pos = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0x0F);
2476 0273 7b03 ld a,(OFST+1,sp)
2477 0275 a40f and a,#15
2478 0277 6b01 ld (OFST-1,sp),a
2479 ; 954 if (reg == 0x00) /* The flag to check is in CRTC Rregister */
2481 0279 0d02 tnz (OFST+0,sp)
2482 027b 2607 jrne L7421
2483 ; 956 reg = CLK->CRTCR;
2485 027d c650c1 ld a,20673
2486 0280 6b02 ld (OFST+0,sp),a
2488 0282 2060 jra L1521
2489 0284 L7421:
2490 ; 958 else if (reg == 0x10) /* The flag to check is in ICKCR register */
2492 0284 7b02 ld a,(OFST+0,sp)
2493 0286 a110 cp a,#16
2494 0288 2607 jrne L3521
2495 ; 960 reg = CLK->ICKCR;
2497 028a c650c2 ld a,20674
2498 028d 6b02 ld (OFST+0,sp),a
2500 028f 2053 jra L1521
2501 0291 L3521:
2502 ; 962 else if (reg == 0x20) /* The flag to check is in CCOR register */
2504 0291 7b02 ld a,(OFST+0,sp)
2505 0293 a120 cp a,#32
2506 0295 2607 jrne L7521
2507 ; 964 reg = CLK->CCOR;
2509 0297 c650c5 ld a,20677
2510 029a 6b02 ld (OFST+0,sp),a
2512 029c 2046 jra L1521
2513 029e L7521:
2514 ; 966 else if (reg == 0x30) /* The flag to check is in ECKCR register */
2516 029e 7b02 ld a,(OFST+0,sp)
2517 02a0 a130 cp a,#48
2518 02a2 2607 jrne L3621
2519 ; 968 reg = CLK->ECKCR;
2521 02a4 c650c6 ld a,20678
2522 02a7 6b02 ld (OFST+0,sp),a
2524 02a9 2039 jra L1521
2525 02ab L3621:
2526 ; 970 else if (reg == 0x40) /* The flag to check is in SWCR register */
2528 02ab 7b02 ld a,(OFST+0,sp)
2529 02ad a140 cp a,#64
2530 02af 2607 jrne L7621
2531 ; 972 reg = CLK->SWCR;
2533 02b1 c650c9 ld a,20681
2534 02b4 6b02 ld (OFST+0,sp),a
2536 02b6 202c jra L1521
2537 02b8 L7621:
2538 ; 974 else if (reg == 0x50) /* The flag to check is in CSSR register */
2540 02b8 7b02 ld a,(OFST+0,sp)
2541 02ba a150 cp a,#80
2542 02bc 2607 jrne L3721
2543 ; 976 reg = CLK->CSSR;
2545 02be c650ca ld a,20682
2546 02c1 6b02 ld (OFST+0,sp),a
2548 02c3 201f jra L1521
2549 02c5 L3721:
2550 ; 978 else if (reg == 0x70) /* The flag to check is in REGCSR register */
2552 02c5 7b02 ld a,(OFST+0,sp)
2553 02c7 a170 cp a,#112
2554 02c9 2607 jrne L7721
2555 ; 980 reg = CLK->REGCSR;
2557 02cb c650cf ld a,20687
2558 02ce 6b02 ld (OFST+0,sp),a
2560 02d0 2012 jra L1521
2561 02d2 L7721:
2562 ; 982 else if (reg == 0x80) /* The flag to check is in CSSLSE_CSRregister */
2564 02d2 7b02 ld a,(OFST+0,sp)
2565 02d4 a180 cp a,#128
2566 02d6 2607 jrne L3031
2567 ; 984 reg = CSSLSE->CSR;
2569 02d8 c65190 ld a,20880
2570 02db 6b02 ld (OFST+0,sp),a
2572 02dd 2005 jra L1521
2573 02df L3031:
2574 ; 988 reg = CLK->CBEEPR;
2576 02df c650cb ld a,20683
2577 02e2 6b02 ld (OFST+0,sp),a
2578 02e4 L1521:
2579 ; 992 if ((reg & (uint8_t)((uint8_t)1 << (uint8_t)pos)) != (uint8_t)RESET)
2581 02e4 7b01 ld a,(OFST-1,sp)
2582 02e6 5f clrw x
2583 02e7 97 ld xl,a
2584 02e8 a601 ld a,#1
2585 02ea 5d tnzw x
2586 02eb 2704 jreq L211
2587 02ed L411:
2588 02ed 48 sll a
2589 02ee 5a decw x
2590 02ef 26fc jrne L411
2591 02f1 L211:
2592 02f1 1402 and a,(OFST+0,sp)
2593 02f3 2706 jreq L7031
2594 ; 994 bitstatus = SET;
2596 02f5 a601 ld a,#1
2597 02f7 6b02 ld (OFST+0,sp),a
2599 02f9 2002 jra L1131
2600 02fb L7031:
2601 ; 998 bitstatus = RESET;
2603 02fb 0f02 clr (OFST+0,sp)
2604 02fd L1131:
2605 ; 1002 return((FlagStatus)bitstatus);
2607 02fd 7b02 ld a,(OFST+0,sp)
2610 02ff 5b03 addw sp,#3
2611 0301 81 ret
2634 ; 1010 void CLK_ClearFlag(void)
2634 ; 1011 {
2635 switch .text
2636 0302 _CLK_ClearFlag:
2640 ; 1014 CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
2642 0302 72175190 bres 20880,#3
2643 ; 1015 }
2646 0306 81 ret
2692 ; 1026 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
2692 ; 1027 {
2693 switch .text
2694 0307 _CLK_GetITStatus:
2696 0307 88 push a
2697 0308 88 push a
2698 00000001 OFST: set 1
2701 ; 1029 ITStatus bitstatus = RESET;
2703 ; 1032 assert_param(IS_CLK_IT(CLK_IT));
2705 ; 1034 if (CLK_IT == CLK_IT_SWIF)
2707 0309 a11c cp a,#28
2708 030b 2611 jrne L5431
2709 ; 1037 if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
2711 030d c450c9 and a,20681
2712 0310 a10c cp a,#12
2713 0312 2606 jrne L7431
2714 ; 1039 bitstatus = SET;
2716 0314 a601 ld a,#1
2717 0316 6b01 ld (OFST+0,sp),a
2719 0318 202e jra L3531
2720 031a L7431:
2721 ; 1043 bitstatus = RESET;
2723 031a 0f01 clr (OFST+0,sp)
2724 031c 202a jra L3531
2725 031e L5431:
2726 ; 1046 else if (CLK_IT == CLK_IT_LSECSSF)
2728 031e 7b02 ld a,(OFST+1,sp)
2729 0320 a12c cp a,#44
2730 0322 2613 jrne L5531
2731 ; 1049 if ((CSSLSE->CSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
2733 0324 c65190 ld a,20880
2734 0327 1402 and a,(OFST+1,sp)
2735 0329 a10c cp a,#12
2736 032b 2606 jrne L7531
2737 ; 1051 bitstatus = SET;
2739 032d a601 ld a,#1
2740 032f 6b01 ld (OFST+0,sp),a
2742 0331 2015 jra L3531
2743 0333 L7531:
2744 ; 1055 bitstatus = RESET;
2746 0333 0f01 clr (OFST+0,sp)
2747 0335 2011 jra L3531
2748 0337 L5531:
2749 ; 1061 if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
2751 0337 c650ca ld a,20682
2752 033a 1402 and a,(OFST+1,sp)
2753 033c a10c cp a,#12
2754 033e 2606 jrne L5631
2755 ; 1063 bitstatus = SET;
2757 0340 a601 ld a,#1
2758 0342 6b01 ld (OFST+0,sp),a
2760 0344 2002 jra L3531
2761 0346 L5631:
2762 ; 1067 bitstatus = RESET;
2764 0346 0f01 clr (OFST+0,sp)
2765 0348 L3531:
2766 ; 1072 return bitstatus;
2768 0348 7b01 ld a,(OFST+0,sp)
2771 034a 85 popw x
2772 034b 81 ret
2808 ; 1083 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
2808 ; 1084 {
2809 switch .text
2810 034c _CLK_ClearITPendingBit:
2814 ; 1087 assert_param(IS_CLK_CLEAR_IT(CLK_IT));
2816 ; 1089 if ((uint8_t)((uint8_t)CLK_IT & (uint8_t)0xF0) == (uint8_t)0x20)
2818 034c a4f0 and a,#240
2819 034e a120 cp a,#32
2820 0350 2606 jrne L7041
2821 ; 1092 CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
2823 0352 72175190 bres 20880,#3
2825 0356 2004 jra L1141
2826 0358 L7041:
2827 ; 1097 CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);
2829 0358 721750c9 bres 20681,#3
2830 035c L1141:
2831 ; 1099 }
2834 035c 81 ret
2859 xdef _SYSDivFactor
2860 xdef _CLK_ClearITPendingBit
2861 xdef _CLK_GetITStatus
2862 xdef _CLK_ClearFlag
2863 xdef _CLK_GetFlagStatus
2864 xdef _CLK_ITConfig
2865 xdef _CLK_MainRegulatorCmd
2866 xdef _CLK_HaltConfig
2867 xdef _CLK_RTCCLKSwitchOnLSEFailureEnable
2868 xdef _CLK_LSEClockSecuritySystemEnable
2869 xdef _CLK_PeripheralClockConfig
2870 xdef _CLK_BEEPClockConfig
2871 xdef _CLK_RTCClockConfig
2872 xdef _CLK_SYSCLKSourceSwitchCmd
2873 xdef _CLK_SYSCLKDivConfig
2874 xdef _CLK_GetClockFreq
2875 xdef _CLK_GetSYSCLKSource
2876 xdef _CLK_SYSCLKSourceConfig
2877 xdef _CLK_CCOConfig
2878 xdef _CLK_ClockSecuritySytemDeglitchCmd
2879 xdef _CLK_ClockSecuritySystemEnable
2880 xdef _CLK_LSEConfig
2881 xdef _CLK_HSEConfig
2882 xdef _CLK_LSICmd
2883 xdef _CLK_AdjustHSICalibrationValue
2884 xdef _CLK_HSICmd
2885 xdef _CLK_DeInit
2886 xref.b c_lreg
2887 xref.b c_x
2906 xref c_ludv
2907 xref c_rtol
2908 xref c_ltor
2909 end
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