📄 stm8l15x_clk.ls
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1143 ; 527 CLK->CKDIVR = (uint8_t)(CLK_SYSCLKDiv);
1145 0130 c750c0 ld 20672,a
1146 ; 528 }
1149 0133 81 ret
1185 ; 535 void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState)
1185 ; 536 {
1186 switch .text
1187 0134 _CLK_SYSCLKSourceSwitchCmd:
1191 ; 538 assert_param(IS_FUNCTIONAL_STATE(NewState));
1193 ; 540 if (NewState != DISABLE)
1195 0134 4d tnz a
1196 0135 2706 jreq L305
1197 ; 543 CLK->SWCR |= CLK_SWCR_SWEN;
1199 0137 721250c9 bset 20681,#1
1201 013b 2004 jra L505
1202 013d L305:
1203 ; 548 CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);
1205 013d 721350c9 bres 20681,#1
1206 0141 L505:
1207 ; 550 }
1210 0141 81 ret
1356 ; 610 void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv)
1356 ; 611 {
1357 switch .text
1358 0142 _CLK_RTCClockConfig:
1360 0142 89 pushw x
1361 00000000 OFST: set 0
1364 ; 613 assert_param(IS_CLK_CLOCK_RTC(CLK_RTCCLKSource));
1366 ; 614 assert_param(IS_CLK_CLOCK_RTC_DIV(CLK_RTCCLKDiv));
1368 ; 617 CLK->CRTCR = (uint8_t)((uint8_t)CLK_RTCCLKSource | (uint8_t)CLK_RTCCLKDiv);
1370 0143 9f ld a,xl
1371 0144 1a01 or a,(OFST+1,sp)
1372 0146 c750c1 ld 20673,a
1373 ; 618 }
1376 0149 85 popw x
1377 014a 81 ret
1443 ; 629 void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource)
1443 ; 630 {
1444 switch .text
1445 014b _CLK_BEEPClockConfig:
1449 ; 632 assert_param(IS_CLK_CLOCK_BEEP(CLK_BEEPCLKSource));
1451 ; 635 CLK->CBEEPR = (uint8_t)(CLK_BEEPCLKSource);
1453 014b c750cb ld 20683,a
1454 ; 637 }
1457 014e 81 ret
1682 ; 671 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
1682 ; 672 {
1683 switch .text
1684 014f _CLK_PeripheralClockConfig:
1686 014f 89 pushw x
1687 0150 88 push a
1688 00000001 OFST: set 1
1691 ; 673 uint8_t reg = 0;
1693 ; 676 assert_param(IS_CLK_PERIPHERAL(CLK_Peripheral));
1695 ; 677 assert_param(IS_FUNCTIONAL_STATE(NewState));
1697 ; 680 reg = (uint8_t)((uint8_t)CLK_Peripheral & (uint8_t)0xF0);
1699 0151 9e ld a,xh
1700 0152 a4f0 and a,#240
1701 0154 6b01 ld (OFST+0,sp),a
1702 ; 682 if ( reg == 0x00)
1704 0156 0d01 tnz (OFST+0,sp)
1705 0158 2635 jrne L527
1706 ; 684 if (NewState != DISABLE)
1708 015a 0d03 tnz (OFST+2,sp)
1709 015c 2719 jreq L727
1710 ; 687 CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
1712 015e 7b02 ld a,(OFST+1,sp)
1713 0160 a40f and a,#15
1714 0162 5f clrw x
1715 0163 97 ld xl,a
1716 0164 a601 ld a,#1
1717 0166 5d tnzw x
1718 0167 2704 jreq L64
1719 0169 L05:
1720 0169 48 sll a
1721 016a 5a decw x
1722 016b 26fc jrne L05
1723 016d L64:
1724 016d ca50c3 or a,20675
1725 0170 c750c3 ld 20675,a
1727 0173 acf901f9 jpf L337
1728 0177 L727:
1729 ; 692 CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
1731 0177 7b02 ld a,(OFST+1,sp)
1732 0179 a40f and a,#15
1733 017b 5f clrw x
1734 017c 97 ld xl,a
1735 017d a601 ld a,#1
1736 017f 5d tnzw x
1737 0180 2704 jreq L25
1738 0182 L45:
1739 0182 48 sll a
1740 0183 5a decw x
1741 0184 26fc jrne L45
1742 0186 L25:
1743 0186 43 cpl a
1744 0187 c450c3 and a,20675
1745 018a c750c3 ld 20675,a
1746 018d 206a jra L337
1747 018f L527:
1748 ; 695 else if (reg == 0x10)
1750 018f 7b01 ld a,(OFST+0,sp)
1751 0191 a110 cp a,#16
1752 0193 2633 jrne L537
1753 ; 697 if (NewState != DISABLE)
1755 0195 0d03 tnz (OFST+2,sp)
1756 0197 2717 jreq L737
1757 ; 700 CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
1759 0199 7b02 ld a,(OFST+1,sp)
1760 019b a40f and a,#15
1761 019d 5f clrw x
1762 019e 97 ld xl,a
1763 019f a601 ld a,#1
1764 01a1 5d tnzw x
1765 01a2 2704 jreq L65
1766 01a4 L06:
1767 01a4 48 sll a
1768 01a5 5a decw x
1769 01a6 26fc jrne L06
1770 01a8 L65:
1771 01a8 ca50c4 or a,20676
1772 01ab c750c4 ld 20676,a
1774 01ae 2049 jra L337
1775 01b0 L737:
1776 ; 705 CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
1778 01b0 7b02 ld a,(OFST+1,sp)
1779 01b2 a40f and a,#15
1780 01b4 5f clrw x
1781 01b5 97 ld xl,a
1782 01b6 a601 ld a,#1
1783 01b8 5d tnzw x
1784 01b9 2704 jreq L26
1785 01bb L46:
1786 01bb 48 sll a
1787 01bc 5a decw x
1788 01bd 26fc jrne L46
1789 01bf L26:
1790 01bf 43 cpl a
1791 01c0 c450c4 and a,20676
1792 01c3 c750c4 ld 20676,a
1793 01c6 2031 jra L337
1794 01c8 L537:
1795 ; 710 if (NewState != DISABLE)
1797 01c8 0d03 tnz (OFST+2,sp)
1798 01ca 2717 jreq L547
1799 ; 713 CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
1801 01cc 7b02 ld a,(OFST+1,sp)
1802 01ce a40f and a,#15
1803 01d0 5f clrw x
1804 01d1 97 ld xl,a
1805 01d2 a601 ld a,#1
1806 01d4 5d tnzw x
1807 01d5 2704 jreq L66
1808 01d7 L07:
1809 01d7 48 sll a
1810 01d8 5a decw x
1811 01d9 26fc jrne L07
1812 01db L66:
1813 01db ca50d0 or a,20688
1814 01de c750d0 ld 20688,a
1816 01e1 2016 jra L337
1817 01e3 L547:
1818 ; 718 CLK->PCKENR3 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
1820 01e3 7b02 ld a,(OFST+1,sp)
1821 01e5 a40f and a,#15
1822 01e7 5f clrw x
1823 01e8 97 ld xl,a
1824 01e9 a601 ld a,#1
1825 01eb 5d tnzw x
1826 01ec 2704 jreq L27
1827 01ee L47:
1828 01ee 48 sll a
1829 01ef 5a decw x
1830 01f0 26fc jrne L47
1831 01f2 L27:
1832 01f2 43 cpl a
1833 01f3 c450d0 and a,20688
1834 01f6 c750d0 ld 20688,a
1835 01f9 L337:
1836 ; 721 }
1839 01f9 5b03 addw sp,#3
1840 01fb 81 ret
1864 ; 759 void CLK_LSEClockSecuritySystemEnable(void)
1864 ; 760 {
1865 switch .text
1866 01fc _CLK_LSEClockSecuritySystemEnable:
1870 ; 762 CSSLSE->CSR |= CSSLSE_CSR_CSSEN;
1872 01fc 72105190 bset 20880,#0
1873 ; 763 }
1876 0200 81 ret
1900 ; 771 void CLK_RTCCLKSwitchOnLSEFailureEnable(void)
1900 ; 772 {
1901 switch .text
1902 0201 _CLK_RTCCLKSwitchOnLSEFailureEnable:
1906 ; 774 CSSLSE->CSR |= CSSLSE_CSR_SWITCHEN;
1908 0201 72125190 bset 20880,#1
1909 ; 775 }
1912 0205 81 ret
1987 ; 801 void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState)
1987 ; 802 {
1988 switch .text
1989 0206 _CLK_HaltConfig:
1991 0206 89 pushw x
1992 00000000 OFST: set 0
1995 ; 804 assert_param(IS_CLK_HALT(CLK_Halt));
1997 ; 805 assert_param(IS_FUNCTIONAL_STATE(NewState));
1999 ; 807 if (NewState != DISABLE)
2001 0207 9f ld a,xl
2002 0208 4d tnz a
2003 0209 2709 jreq L5201
2004 ; 809 CLK->ICKCR |= (uint8_t)(CLK_Halt);
2006 020b 9e ld a,xh
2007 020c ca50c2 or a,20674
2008 020f c750c2 ld 20674,a
2010 0212 2009 jra L7201
2011 0214 L5201:
2012 ; 813 CLK->ICKCR &= (uint8_t)(~CLK_Halt);
2014 0214 7b01 ld a,(OFST+1,sp)
2015 0216 43 cpl a
2016 0217 c450c2 and a,20674
2017 021a c750c2 ld 20674,a
2018 021d L7201:
2019 ; 815 }
2022 021d 85 popw x
2023 021e 81 ret
2059 ; 825 void CLK_MainRegulatorCmd(FunctionalState NewState)
2059 ; 826 {
2060 switch .text
2061 021f _CLK_MainRegulatorCmd:
2065 ; 828 assert_param(IS_FUNCTIONAL_STATE(NewState));
2067 ; 830 if (NewState != DISABLE)
2069 021f 4d tnz a
2070 0220 2706 jreq L7401
2071 ; 833 CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF);
2073 0222 721350cf bres 20687,#1
2075 0226 2004 jra L1501
2076 0228 L7401:
2077 ; 838 CLK->REGCSR |= CLK_REGCSR_REGOFF;
2079 0228 721250cf bset 20687,#1
2080 022c L1501:
2081 ; 840 }
2084 022c 81 ret
2156 ; 869 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
2156 ; 870 {
2157 switch .text
2158 022d _CLK_ITConfig:
2160 022d 89 pushw x
2161 00000000 OFST: set 0
2164 ; 873 assert_param(IS_CLK_IT(CLK_IT));
2166 ; 874 assert_param(IS_FUNCTIONAL_STATE(NewState));
2168 ; 876 if (NewState != DISABLE)
2170 022e 9f ld a,xl
2171 022f 4d tnz a
2172 0230 271d jreq L7011
2173 ; 878 if (CLK_IT == CLK_IT_SWIF)
2175 0232 9e ld a,xh
2176 0233 a11c cp a,#28
2177 0235 2606 jrne L1111
2178 ; 881 CLK->SWCR |= CLK_SWCR_SWIEN;
2180 0237 721450c9 bset 20681,#2
2182 023b 202e jra L1211
2183 023d L1111:
2184 ; 883 else if (CLK_IT == CLK_IT_LSECSSF)
2186 023d 7b01 ld a,(OFST+1,sp)
2187 023f a12c cp a,#44
2188 0241 2606 jrne L5111
2189 ; 886 CSSLSE->CSR |= CSSLSE_CSR_CSSIE;
2191 0243 72145190 bset 20880,#2
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