📄 stm8l15x_clk.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
15 .const: section .text
16 0000 _SYSDivFactor:
17 0000 01 dc.b 1
18 0001 02 dc.b 2
19 0002 04 dc.b 4
20 0003 08 dc.b 8
21 0004 10 dc.b 16
50 ; 114 void CLK_DeInit(void)
50 ; 115 {
52 switch .text
53 0000 _CLK_DeInit:
57 ; 116 CLK->ICKCR = CLK_ICKCR_RESET_VALUE;
59 0000 351150c2 mov 20674,#17
60 ; 117 CLK->ECKCR = CLK_ECKCR_RESET_VALUE;
62 0004 725f50c6 clr 20678
63 ; 118 CLK->CRTCR = CLK_CRTCR_RESET_VALUE;
65 0008 725f50c1 clr 20673
66 ; 119 CLK->CBEEPR = CLK_CBEEPR_RESET_VALUE;
68 000c 725f50cb clr 20683
69 ; 120 CLK->SWR = CLK_SWR_RESET_VALUE;
71 0010 350150c8 mov 20680,#1
72 ; 121 CLK->SWCR = CLK_SWCR_RESET_VALUE;
74 0014 725f50c9 clr 20681
75 ; 122 CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
77 0018 350350c0 mov 20672,#3
78 ; 123 CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
80 001c 725f50c3 clr 20675
81 ; 124 CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
83 0020 358050c4 mov 20676,#128
84 ; 125 CLK->PCKENR3 = CLK_PCKENR3_RESET_VALUE;
86 0024 725f50d0 clr 20688
87 ; 126 CLK->CSSR = CLK_CSSR_RESET_VALUE;
89 0028 725f50ca clr 20682
90 ; 127 CLK->CCOR = CLK_CCOR_RESET_VALUE;
92 002c 725f50c5 clr 20677
93 ; 128 CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
95 0030 725f50cd clr 20685
96 ; 129 CLK->HSICALR = CLK_HSICALR_RESET_VALUE;
98 0034 725f50cc clr 20684
99 ; 130 CLK->HSIUNLCKR = CLK_HSIUNLCKR_RESET_VALUE;
101 0038 725f50ce clr 20686
102 ; 131 CLK->REGCSR = CLK_REGCSR_RESET_VALUE;
104 003c 35b950cf mov 20687,#185
105 ; 132 }
108 0040 81 ret
163 ; 154 void CLK_HSICmd(FunctionalState NewState)
163 ; 155 {
164 switch .text
165 0041 _CLK_HSICmd:
169 ; 157 assert_param(IS_FUNCTIONAL_STATE(NewState));
171 ; 159 if (NewState != DISABLE)
173 0041 4d tnz a
174 0042 2706 jreq L74
175 ; 162 CLK->ICKCR |= CLK_ICKCR_HSION;
177 0044 721050c2 bset 20674,#0
179 0048 2004 jra L15
180 004a L74:
181 ; 167 CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_HSION);
183 004a 721150c2 bres 20674,#0
184 004e L15:
185 ; 169 }
188 004e 81 ret
224 ; 182 void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue)
224 ; 183 {
225 switch .text
226 004f _CLK_AdjustHSICalibrationValue:
230 ; 185 CLK->HSIUNLCKR = 0xAC;
232 004f 35ac50ce mov 20686,#172
233 ; 186 CLK->HSIUNLCKR = 0x35;
235 0053 353550ce mov 20686,#53
236 ; 189 CLK->HSITRIMR = (uint8_t)CLK_HSICalibrationValue;
238 0057 c750cd ld 20685,a
239 ; 190 }
242 005a 81 ret
277 ; 206 void CLK_LSICmd(FunctionalState NewState)
277 ; 207 {
278 switch .text
279 005b _CLK_LSICmd:
283 ; 210 assert_param(IS_FUNCTIONAL_STATE(NewState));
285 ; 212 if (NewState != DISABLE)
287 005b 4d tnz a
288 005c 2706 jreq L701
289 ; 215 CLK->ICKCR |= CLK_ICKCR_LSION;
291 005e 721450c2 bset 20674,#2
293 0062 2004 jra L111
294 0064 L701:
295 ; 220 CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_LSION);
297 0064 721550c2 bres 20674,#2
298 0068 L111:
299 ; 222 }
302 0068 81 ret
364 ; 243 void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE)
364 ; 244 {
365 switch .text
366 0069 _CLK_HSEConfig:
370 ; 246 assert_param(IS_CLK_HSE(CLK_HSE));
372 ; 250 CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEON;
374 0069 721150c6 bres 20678,#0
375 ; 253 CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEBYP;
377 006d 721950c6 bres 20678,#4
378 ; 256 CLK->ECKCR |= (uint8_t)CLK_HSE;
380 0071 ca50c6 or a,20678
381 0074 c750c6 ld 20678,a
382 ; 257 }
385 0077 81 ret
447 ; 274 void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE)
447 ; 275 {
448 switch .text
449 0078 _CLK_LSEConfig:
453 ; 277 assert_param(IS_CLK_LSE(CLK_LSE));
455 ; 281 CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEON;
457 0078 721550c6 bres 20678,#2
458 ; 284 CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEBYP;
460 007c 721b50c6 bres 20678,#5
461 ; 287 CLK->ECKCR |= (uint8_t)CLK_LSE;
463 0080 ca50c6 or a,20678
464 0083 c750c6 ld 20678,a
465 ; 289 }
468 0086 81 ret
492 ; 300 void CLK_ClockSecuritySystemEnable(void)
492 ; 301 {
493 switch .text
494 0087 _CLK_ClockSecuritySystemEnable:
498 ; 303 CLK->CSSR |= CLK_CSSR_CSSEN;
500 0087 721050ca bset 20682,#0
501 ; 304 }
504 008b 81 ret
540 ; 311 void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState)
540 ; 312 {
541 switch .text
542 008c _CLK_ClockSecuritySytemDeglitchCmd:
546 ; 314 assert_param(IS_FUNCTIONAL_STATE(NewState));
548 ; 316 if (NewState != DISABLE)
550 008c 4d tnz a
551 008d 2706 jreq L122
552 ; 319 CLK->CSSR |= CLK_CSSR_CSSDGON;
554 008f 721850ca bset 20682,#4
556 0093 2004 jra L322
557 0095 L122:
558 ; 324 CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDGON);
560 0095 721950ca bres 20682,#4
561 0099 L322:
562 ; 326 }
565 0099 81 ret
706 ; 350 void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv)
706 ; 351 {
707 switch .text
708 009a _CLK_CCOConfig:
710 009a 89 pushw x
711 00000000 OFST: set 0
714 ; 353 assert_param(IS_CLK_OUTPUT(CLK_CCOSource));
716 ; 354 assert_param(IS_CLK_OUTPUT_DIVIDER(CLK_CCODiv));
718 ; 357 CLK->CCOR = (uint8_t)((uint8_t)CLK_CCOSource | (uint8_t)CLK_CCODiv);
720 009b 9f ld a,xl
721 009c 1a01 or a,(OFST+1,sp)
722 009e c750c5 ld 20677,a
723 ; 358 }
726 00a1 85 popw x
727 00a2 81 ret
801 ; 410 void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource)
801 ; 411 {
802 switch .text
803 00a3 _CLK_SYSCLKSourceConfig:
807 ; 413 assert_param(IS_CLK_SOURCE(CLK_SYSCLKSource));
809 ; 416 CLK->SWR = (uint8_t)CLK_SYSCLKSource;
811 00a3 c750c8 ld 20680,a
812 ; 417 }
815 00a6 81 ret
840 ; 429 CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void)
840 ; 430 {
841 switch .text
842 00a7 _CLK_GetSYSCLKSource:
846 ; 431 return ((CLK_SYSCLKSource_TypeDef)(CLK->SCSR));
848 00a7 c650c7 ld a,20679
851 00aa 81 ret
923 ; 472 uint32_t CLK_GetClockFreq(void)
923 ; 473 {
924 switch .text
925 00ab _CLK_GetClockFreq:
927 00ab 5209 subw sp,#9
928 00000009 OFST: set 9
931 ; 474 uint32_t clockfrequency = 0;
933 ; 475 uint32_t sourcefrequency = 0;
935 00ad ae0000 ldw x,#0
936 00b0 1f07 ldw (OFST-2,sp),x
937 00b2 ae0000 ldw x,#0
938 00b5 1f05 ldw (OFST-4,sp),x
939 ; 476 CLK_SYSCLKSource_TypeDef clocksource = CLK_SYSCLKSource_HSI;
941 ; 477 uint8_t tmp = 0, presc = 0;
945 ; 480 clocksource = (CLK_SYSCLKSource_TypeDef)CLK->SCSR;
947 00b7 c650c7 ld a,20679
948 00ba 6b09 ld (OFST+0,sp),a
949 ; 482 if ( clocksource == CLK_SYSCLKSource_HSI)
951 00bc 7b09 ld a,(OFST+0,sp)
952 00be a101 cp a,#1
953 00c0 260c jrne L704
954 ; 484 sourcefrequency = HSI_VALUE;
956 00c2 ae2400 ldw x,#9216
957 00c5 1f07 ldw (OFST-2,sp),x
958 00c7 ae00f4 ldw x,#244
959 00ca 1f05 ldw (OFST-4,sp),x
961 00cc 2022 jra L114
962 00ce L704:
963 ; 486 else if ( clocksource == CLK_SYSCLKSource_LSI)
965 00ce 7b09 ld a,(OFST+0,sp)
966 00d0 a102 cp a,#2
967 00d2 260c jrne L314
968 ; 488 sourcefrequency = LSI_VALUE;
970 00d4 ae9470 ldw x,#38000
971 00d7 1f07 ldw (OFST-2,sp),x
972 00d9 ae0000 ldw x,#0
973 00dc 1f05 ldw (OFST-4,sp),x
975 00de 2010 jra L114
976 00e0 L314:
977 ; 490 else if ( clocksource == CLK_SYSCLKSource_HSE)
979 00e0 7b09 ld a,(OFST+0,sp)
980 00e2 a104 cp a,#4
981 00e4 260a jrne L714
982 ; 492 sourcefrequency = HSE_VALUE;
984 00e6 ae2400 ldw x,#9216
985 00e9 1f07 ldw (OFST-2,sp),x
986 00eb ae00f4 ldw x,#244
987 00ee 1f05 ldw (OFST-4,sp),x
989 00f0 L714:
990 ; 496 clockfrequency = LSE_VALUE;
992 00f0 L114:
993 ; 500 tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_CKM);
995 00f0 c650c0 ld a,20672
996 00f3 a407 and a,#7
997 00f5 6b09 ld (OFST+0,sp),a
998 ; 501 presc = SYSDivFactor[tmp];
1000 00f7 7b09 ld a,(OFST+0,sp)
1001 00f9 5f clrw x
1002 00fa 97 ld xl,a
1003 00fb d60000 ld a,(_SYSDivFactor,x)
1004 00fe 6b09 ld (OFST+0,sp),a
1005 ; 504 clockfrequency = sourcefrequency / presc;
1007 0100 7b09 ld a,(OFST+0,sp)
1008 0102 b703 ld c_lreg+3,a
1009 0104 3f02 clr c_lreg+2
1010 0106 3f01 clr c_lreg+1
1011 0108 3f00 clr c_lreg
1012 010a 96 ldw x,sp
1013 010b 1c0001 addw x,#OFST-8
1014 010e cd0000 call c_rtol
1016 0111 96 ldw x,sp
1017 0112 1c0005 addw x,#OFST-4
1018 0115 cd0000 call c_ltor
1020 0118 96 ldw x,sp
1021 0119 1c0001 addw x,#OFST-8
1022 011c cd0000 call c_ludv
1024 011f 96 ldw x,sp
1025 0120 1c0005 addw x,#OFST-4
1026 0123 cd0000 call c_rtol
1028 ; 506 return((uint32_t)clockfrequency);
1030 0126 96 ldw x,sp
1031 0127 1c0005 addw x,#OFST-4
1032 012a cd0000 call c_ltor
1036 012d 5b09 addw sp,#9
1037 012f 81 ret
1135 ; 522 void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv)
1135 ; 523 {
1136 switch .text
1137 0130 _CLK_SYSCLKDivConfig:
1141 ; 525 assert_param(IS_CLK_SYSTEM_DIVIDER(CLK_SYSCLKDiv));
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