📄 stm8l15x_tim2.ls
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3907 043f c65257 ld a,21079
3908 0442 1403 and a,(OFST+1,sp)
3909 0444 6b02 ld (OFST+0,sp),a
3910 ; 1478 if ((uint8_t)(tim2_flag_l | tim2_flag_h) != 0)
3912 0446 7b01 ld a,(OFST-1,sp)
3913 0448 1a02 or a,(OFST+0,sp)
3914 044a 2706 jreq L7502
3915 ; 1480 bitstatus = SET;
3917 044c a601 ld a,#1
3918 044e 6b02 ld (OFST+0,sp),a
3920 0450 2002 jra L1602
3921 0452 L7502:
3922 ; 1484 bitstatus = RESET;
3924 0452 0f02 clr (OFST+0,sp)
3925 0454 L1602:
3926 ; 1486 return ((FlagStatus)bitstatus);
3928 0454 7b02 ld a,(OFST+0,sp)
3931 0456 5b04 addw sp,#4
3932 0458 81 ret
3967 ; 1500 void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG)
3967 ; 1501 {
3968 switch .text
3969 0459 _TIM2_ClearFlag:
3971 0459 89 pushw x
3972 00000000 OFST: set 0
3975 ; 1503 assert_param(IS_TIM2_CLEAR_FLAG((uint16_t)TIM2_FLAG));
3977 ; 1505 TIM2->SR1 = (uint8_t)(~(uint8_t)(TIM2_FLAG));
3979 045a 9f ld a,xl
3980 045b 43 cpl a
3981 045c c75256 ld 21078,a
3982 ; 1506 TIM2->SR2 = (uint8_t)(~(uint8_t)((uint16_t)TIM2_FLAG >> 8));
3984 045f 7b01 ld a,(OFST+1,sp)
3985 0461 43 cpl a
3986 0462 c75257 ld 21079,a
3987 ; 1507 }
3990 0465 85 popw x
3991 0466 81 ret
4055 ; 1520 ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT)
4055 ; 1521 {
4056 switch .text
4057 0467 _TIM2_GetITStatus:
4059 0467 88 push a
4060 0468 89 pushw x
4061 00000002 OFST: set 2
4064 ; 1522 ITStatus bitstatus = RESET;
4066 ; 1524 uint8_t TIM2_itStatus = 0x0, TIM2_itEnable = 0x0;
4070 ; 1527 assert_param(IS_TIM2_GET_IT(TIM2_IT));
4072 ; 1529 TIM2_itStatus = (uint8_t)(TIM2->SR1 & (uint8_t)TIM2_IT);
4074 0469 c45256 and a,21078
4075 046c 6b01 ld (OFST-1,sp),a
4076 ; 1531 TIM2_itEnable = (uint8_t)(TIM2->IER & (uint8_t)TIM2_IT);
4078 046e c65255 ld a,21077
4079 0471 1403 and a,(OFST+1,sp)
4080 0473 6b02 ld (OFST+0,sp),a
4081 ; 1533 if ((TIM2_itStatus != (uint8_t)RESET ) && (TIM2_itEnable != (uint8_t)RESET))
4083 0475 0d01 tnz (OFST-1,sp)
4084 0477 270a jreq L3312
4086 0479 0d02 tnz (OFST+0,sp)
4087 047b 2706 jreq L3312
4088 ; 1535 bitstatus = (ITStatus)SET;
4090 047d a601 ld a,#1
4091 047f 6b02 ld (OFST+0,sp),a
4093 0481 2002 jra L5312
4094 0483 L3312:
4095 ; 1539 bitstatus = (ITStatus)RESET;
4097 0483 0f02 clr (OFST+0,sp)
4098 0485 L5312:
4099 ; 1541 return ((ITStatus)bitstatus);
4101 0485 7b02 ld a,(OFST+0,sp)
4104 0487 5b03 addw sp,#3
4105 0489 81 ret
4141 ; 1555 void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT)
4141 ; 1556 {
4142 switch .text
4143 048a _TIM2_ClearITPendingBit:
4147 ; 1558 assert_param(IS_TIM2_IT(TIM2_IT));
4149 ; 1561 TIM2->SR1 = (uint8_t)(~(uint8_t)TIM2_IT);
4151 048a 43 cpl a
4152 048b c75256 ld 21078,a
4153 ; 1562 }
4156 048e 81 ret
4229 ; 1575 void TIM2_DMACmd( TIM2_DMASource_TypeDef TIM2_DMASource, FunctionalState NewState)
4229 ; 1576 {
4230 switch .text
4231 048f _TIM2_DMACmd:
4233 048f 89 pushw x
4234 00000000 OFST: set 0
4237 ; 1578 assert_param(IS_FUNCTIONAL_STATE(NewState));
4239 ; 1579 assert_param(IS_TIM2_DMA_SOURCE(TIM2_DMASource));
4241 ; 1581 if (NewState != DISABLE)
4243 0490 9f ld a,xl
4244 0491 4d tnz a
4245 0492 2709 jreq L1122
4246 ; 1584 TIM2->DER |= TIM2_DMASource;
4248 0494 9e ld a,xh
4249 0495 ca5254 or a,21076
4250 0498 c75254 ld 21076,a
4252 049b 2009 jra L3122
4253 049d L1122:
4254 ; 1589 TIM2->DER &= (uint8_t)(~TIM2_DMASource);
4256 049d 7b01 ld a,(OFST+1,sp)
4257 049f 43 cpl a
4258 04a0 c45254 and a,21076
4259 04a3 c75254 ld 21076,a
4260 04a6 L3122:
4261 ; 1591 }
4264 04a6 85 popw x
4265 04a7 81 ret
4300 ; 1599 void TIM2_SelectCCDMA(FunctionalState NewState)
4300 ; 1600 {
4301 switch .text
4302 04a8 _TIM2_SelectCCDMA:
4306 ; 1602 assert_param(IS_FUNCTIONAL_STATE(NewState));
4308 ; 1604 if (NewState != DISABLE)
4310 04a8 4d tnz a
4311 04a9 2706 jreq L3322
4312 ; 1607 TIM2->CR2 |= TIM_CR2_CCDS;
4314 04ab 72165251 bset 21073,#3
4316 04af 2004 jra L5322
4317 04b1 L3322:
4318 ; 1612 TIM2->CR2 &= (uint8_t)(~TIM_CR2_CCDS);
4320 04b1 72175251 bres 21073,#3
4321 04b5 L5322:
4322 ; 1614 }
4325 04b5 81 ret
4349 ; 1638 void TIM2_InternalClockConfig(void)
4349 ; 1639 {
4350 switch .text
4351 04b6 _TIM2_InternalClockConfig:
4355 ; 1641 TIM2->SMCR &= (uint8_t)(~TIM_SMCR_SMS);
4357 04b6 c65252 ld a,21074
4358 04b9 a4f8 and a,#248
4359 04bb c75252 ld 21074,a
4360 ; 1642 }
4363 04be 81 ret
4452 ; 1659 void TIM2_TIxExternalClockConfig(TIM2_TIxExternalCLK1Source_TypeDef TIM2_TIxExternalCLKSource,
4452 ; 1660 TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
4452 ; 1661 uint8_t ICFilter)
4452 ; 1662 {
4453 switch .text
4454 04bf _TIM2_TIxExternalClockConfig:
4456 04bf 89 pushw x
4457 00000000 OFST: set 0
4460 ; 1664 assert_param(IS_TIM2_TIXCLK_SOURCE(TIM2_TIxExternalCLKSource));
4462 ; 1665 assert_param(IS_TIM2_IC_POLARITY(TIM2_ICPolarity));
4464 ; 1666 assert_param(IS_TIM2_IC_FILTER(ICFilter));
4466 ; 1669 if (TIM2_TIxExternalCLKSource == TIM2_TIxExternalCLK1Source_TI2)
4468 04c0 9e ld a,xh
4469 04c1 a160 cp a,#96
4470 04c3 260f jrne L7032
4471 ; 1671 TI2_Config(TIM2_ICPolarity, TIM2_ICSelection_DirectTI, ICFilter);
4473 04c5 7b05 ld a,(OFST+5,sp)
4474 04c7 88 push a
4475 04c8 ae0001 ldw x,#1
4476 04cb 7b03 ld a,(OFST+3,sp)
4477 04cd 95 ld xh,a
4478 04ce cd064b call L5_TI2_Config
4480 04d1 84 pop a
4482 04d2 200d jra L1132
4483 04d4 L7032:
4484 ; 1675 TI1_Config(TIM2_ICPolarity, TIM2_ICSelection_DirectTI, ICFilter);
4486 04d4 7b05 ld a,(OFST+5,sp)
4487 04d6 88 push a
4488 04d7 ae0001 ldw x,#1
4489 04da 7b03 ld a,(OFST+3,sp)
4490 04dc 95 ld xh,a
4491 04dd cd060e call L3_TI1_Config
4493 04e0 84 pop a
4494 04e1 L1132:
4495 ; 1679 TIM2_SelectInputTrigger((TIM2_TRGSelection_TypeDef)TIM2_TIxExternalCLKSource);
4497 04e1 7b01 ld a,(OFST+1,sp)
4498 04e3 ad4b call _TIM2_SelectInputTrigger
4500 ; 1682 TIM2->SMCR |= (uint8_t)(TIM2_SlaveMode_External1);
4502 04e5 c65252 ld a,21074
4503 04e8 aa07 or a,#7
4504 04ea c75252 ld 21074,a
4505 ; 1683 }
4508 04ed 85 popw x
4509 04ee 81 ret
4626 ; 1701 void TIM2_ETRClockMode1Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
4626 ; 1702 TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
4626 ; 1703 uint8_t ExtTRGFilter)
4626 ; 1704 {
4627 switch .text
4628 04ef _TIM2_ETRClockMode1Config:
4630 04ef 89 pushw x
4631 00000000 OFST: set 0
4634 ; 1706 TIM2_ETRConfig(TIM2_ExtTRGPrescaler, TIM2_ExtTRGPolarity, ExtTRGFilter);
4636 04f0 7b05 ld a,(OFST+5,sp)
4637 04f2 88 push a
4638 04f3 9f ld a,xl
4639 04f4 97 ld xl,a
4640 04f5 7b02 ld a,(OFST+2,sp)
4641 04f7 95 ld xh,a
4642 04f8 cd058c call _TIM2_ETRConfig
4644 04fb 84 pop a
4645 ; 1709 TIM2->SMCR &= (uint8_t)(~TIM_SMCR_SMS);
4647 04fc c65252 ld a,21074
4648 04ff a4f8 and a,#248
4649 0501 c75252 ld 21074,a
4650 ; 1710 TIM2->SMCR |= (uint8_t)(TIM2_SlaveMode_External1);
4652 0504 c65252 ld a,21074
4653 0507 aa07 or a,#7
4654 0509 c75252 ld 21074,a
4655 ; 1713 TIM2->SMCR &= (uint8_t)(~TIM_SMCR_TS);
4657 050c c65252 ld a,21074
4658 050f a48f and a,#143
4659 0511 c75252 ld 21074,a
4660 ; 1714 TIM2->SMCR |= (uint8_t)((TIM2_TRGSelection_TypeDef)TIM2_TRGSelection_ETRF);
4662 0514 c65252 ld a,21074
4663 0517 aa70 or a,#112
4664 0519 c75252 ld 21074,a
4665 ; 1715 }
4668 051c 85 popw x
4669 051d 81 ret
4727 ; 1733 void TIM2_ETRClockMode2Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
4727 ; 1734 TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
4727 ; 1735 uint8_t ExtTRGFilter)
4727 ; 1736 {
4728 switch .text
4729 051e _TIM2_ETRClockMode2Config:
4731 051e 89 pushw x
4732 00000000 OFST: set 0
4735 ; 1738 TIM2_ETRConfig(TIM2_ExtTRGPrescaler, TIM2_ExtTRGPolarity, ExtTRGFilter);
4737 051f 7b05 ld a,(OFST+5,sp)
4738 0521 88 push a
4739 0522 9f ld a,xl
4740 0523 97 ld xl,a
4741 0524 7b02 ld a,(OFST+2,sp)
4742 0526 95 ld xh,a
4743 0527 ad63 call _TIM2_ETRConfig
4745 0529 84 pop a
4746 ; 1741 TIM2->ETR |= TIM_ETR_ECE ;
4748 052a 721c5253 bset 21075,#6
4749 ; 1742 }
4752 052e 85 popw x
4753 052f 81 ret
4869 ; 1793 void TIM2_SelectInputTrigger(TIM2_TRGSelection_TypeDef TIM2_InputTriggerSource)
4869 ; 1794 {
4870 switch .text
4871 0530 _TIM2_SelectInputTrigger:
4873 0530 88 push a
4874 0531 88 push a
4875 00000001 OFST: set 1
4878 ; 1795 uint8_t tmpsmcr = 0;
4880 ; 1798 assert_param(IS_TIM2_TRIGGER_SELECTION(TIM2_InputTriggerSource));
4882 ; 1800 tmpsmcr = TIM2->SMCR;
4884 0532 c65252 ld a,21074
4885 0535 6b01 ld (OFST+0,sp),a
4886 ; 1803 tmpsmcr &= (uint8_t)(~TIM_SMCR_TS);
4888 0537 7b01 ld a,(OFST+0,sp)
4889 0539 a48f and a,#143
4890 053b 6b01 ld (OFST+0,sp),a
4891 ; 1804 tmpsmcr |= (uint8_t)TIM2_InputTriggerSource;
4893 053d 7b01 ld a,(OFST+0,sp)
4894 053f 1a02 or a,(OFST+1,sp)
4895 0541 6b01 ld (OFST+0,sp),a
4896 ; 1806 TIM2->SMCR = (uint8_t)tmpsmcr;
4898 0543 7b01 ld a,(OFST+0,sp)
4899 0545 c75252 ld 21074,a
4900 ; 1807 }
4903 0548 85 popw x
4904 0549 81 ret
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