📄 stm8l15x_tim2.ls
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1037 ; 468 TIM2->CR1 |= TIM_CR1_OPM ;
1039 0122 72165250 bset 21072,#3
1041 0126 2004 jra L524
1042 0128 L324:
1043 ; 472 TIM2->CR1 &= (uint8_t)(~TIM_CR1_OPM);
1045 0128 72175250 bres 21072,#3
1046 012c L524:
1047 ; 474 }
1050 012c 81 ret
1085 ; 482 void TIM2_Cmd(FunctionalState NewState)
1085 ; 483 {
1086 switch .text
1087 012d _TIM2_Cmd:
1091 ; 485 assert_param(IS_FUNCTIONAL_STATE(NewState));
1093 ; 488 if (NewState != DISABLE)
1095 012d 4d tnz a
1096 012e 2706 jreq L544
1097 ; 490 TIM2->CR1 |= TIM_CR1_CEN;
1099 0130 72105250 bset 21072,#0
1101 0134 2004 jra L744
1102 0136 L544:
1103 ; 494 TIM2->CR1 &= (uint8_t)(~TIM_CR1_CEN);
1105 0136 72115250 bres 21072,#0
1106 013a L744:
1107 ; 496 }
1110 013a 81 ret
1308 ; 572 void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode,
1308 ; 573 TIM2_OutputState_TypeDef TIM2_OutputState,
1308 ; 574 uint16_t TIM2_Pulse,
1308 ; 575 TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
1308 ; 576 TIM2_OCIdleState_TypeDef TIM2_OCIdleState)
1308 ; 577 {
1309 switch .text
1310 013b _TIM2_OC1Init:
1312 013b 89 pushw x
1313 013c 88 push a
1314 00000001 OFST: set 1
1317 ; 578 uint8_t tmpccmr1 = 0;
1319 ; 581 assert_param(IS_TIM2_OC_MODE(TIM2_OCMode));
1321 ; 582 assert_param(IS_TIM2_OUTPUT_STATE(TIM2_OutputState));
1323 ; 583 assert_param(IS_TIM2_OC_POLARITY(TIM2_OCPolarity));
1325 ; 584 assert_param(IS_TIM2_OCIDLE_STATE(TIM2_OCIdleState));
1327 ; 586 tmpccmr1 = TIM2->CCMR1;
1329 013d c65259 ld a,21081
1330 0140 6b01 ld (OFST+0,sp),a
1331 ; 589 TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
1333 0142 7211525b bres 21083,#0
1334 ; 591 tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM);
1336 0146 7b01 ld a,(OFST+0,sp)
1337 0148 a48f and a,#143
1338 014a 6b01 ld (OFST+0,sp),a
1339 ; 594 tmpccmr1 |= (uint8_t)TIM2_OCMode;
1341 014c 9e ld a,xh
1342 014d 1a01 or a,(OFST+0,sp)
1343 014f 6b01 ld (OFST+0,sp),a
1344 ; 596 TIM2->CCMR1 = tmpccmr1;
1346 0151 7b01 ld a,(OFST+0,sp)
1347 0153 c75259 ld 21081,a
1348 ; 599 if (TIM2_OutputState == TIM2_OutputState_Enable)
1350 0156 9f ld a,xl
1351 0157 a101 cp a,#1
1352 0159 2606 jrne L365
1353 ; 601 TIM2->CCER1 |= TIM_CCER1_CC1E;
1355 015b 7210525b bset 21083,#0
1357 015f 2004 jra L565
1358 0161 L365:
1359 ; 605 TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
1361 0161 7211525b bres 21083,#0
1362 0165 L565:
1363 ; 609 if (TIM2_OCPolarity == TIM2_OCPolarity_Low)
1365 0165 7b08 ld a,(OFST+7,sp)
1366 0167 a101 cp a,#1
1367 0169 2606 jrne L765
1368 ; 611 TIM2->CCER1 |= TIM_CCER1_CC1P;
1370 016b 7212525b bset 21083,#1
1372 016f 2004 jra L175
1373 0171 L765:
1374 ; 615 TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P);
1376 0171 7213525b bres 21083,#1
1377 0175 L175:
1378 ; 619 if (TIM2_OCIdleState == TIM2_OCIdleState_Set)
1380 0175 7b09 ld a,(OFST+8,sp)
1381 0177 a101 cp a,#1
1382 0179 2606 jrne L375
1383 ; 621 TIM2->OISR |= TIM_OISR_OIS1;
1385 017b 72105266 bset 21094,#0
1387 017f 2004 jra L575
1388 0181 L375:
1389 ; 625 TIM2->OISR &= (uint8_t)(~TIM_OISR_OIS1);
1391 0181 72115266 bres 21094,#0
1392 0185 L575:
1393 ; 629 TIM2->CCR1H = (uint8_t)(TIM2_Pulse >> 8);
1395 0185 7b06 ld a,(OFST+5,sp)
1396 0187 c75261 ld 21089,a
1397 ; 630 TIM2->CCR1L = (uint8_t)(TIM2_Pulse);
1399 018a 7b07 ld a,(OFST+6,sp)
1400 018c c75262 ld 21090,a
1401 ; 631 }
1404 018f 5b03 addw sp,#3
1405 0191 81 ret
1488 ; 658 void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode,
1488 ; 659 TIM2_OutputState_TypeDef TIM2_OutputState,
1488 ; 660 uint16_t TIM2_Pulse,
1488 ; 661 TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
1488 ; 662 TIM2_OCIdleState_TypeDef TIM2_OCIdleState)
1488 ; 663 {
1489 switch .text
1490 0192 _TIM2_OC2Init:
1492 0192 89 pushw x
1493 0193 88 push a
1494 00000001 OFST: set 1
1497 ; 664 uint8_t tmpccmr2 = 0;
1499 ; 667 assert_param(IS_TIM2_OC_MODE(TIM2_OCMode));
1501 ; 668 assert_param(IS_TIM2_OUTPUT_STATE(TIM2_OutputState));
1503 ; 669 assert_param(IS_TIM2_OC_POLARITY(TIM2_OCPolarity));
1505 ; 670 assert_param(IS_TIM2_OCIDLE_STATE(TIM2_OCIdleState));
1507 ; 672 tmpccmr2 = TIM2->CCMR2;
1509 0194 c6525a ld a,21082
1510 0197 6b01 ld (OFST+0,sp),a
1511 ; 675 TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
1513 0199 7219525b bres 21083,#4
1514 ; 678 tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM);
1516 019d 7b01 ld a,(OFST+0,sp)
1517 019f a48f and a,#143
1518 01a1 6b01 ld (OFST+0,sp),a
1519 ; 681 tmpccmr2 |= (uint8_t)TIM2_OCMode;
1521 01a3 9e ld a,xh
1522 01a4 1a01 or a,(OFST+0,sp)
1523 01a6 6b01 ld (OFST+0,sp),a
1524 ; 683 TIM2->CCMR2 = tmpccmr2;
1526 01a8 7b01 ld a,(OFST+0,sp)
1527 01aa c7525a ld 21082,a
1528 ; 686 if (TIM2_OutputState == TIM2_OutputState_Enable)
1530 01ad 9f ld a,xl
1531 01ae a101 cp a,#1
1532 01b0 2606 jrne L146
1533 ; 688 TIM2->CCER1 |= TIM_CCER1_CC2E;
1535 01b2 7218525b bset 21083,#4
1537 01b6 2004 jra L346
1538 01b8 L146:
1539 ; 692 TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
1541 01b8 7219525b bres 21083,#4
1542 01bc L346:
1543 ; 696 if (TIM2_OCPolarity == TIM2_OCPolarity_Low)
1545 01bc 7b08 ld a,(OFST+7,sp)
1546 01be a101 cp a,#1
1547 01c0 2606 jrne L546
1548 ; 698 TIM2->CCER1 |= TIM_CCER1_CC2P;
1550 01c2 721a525b bset 21083,#5
1552 01c6 2004 jra L746
1553 01c8 L546:
1554 ; 702 TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P);
1556 01c8 721b525b bres 21083,#5
1557 01cc L746:
1558 ; 707 if (TIM2_OCIdleState == TIM2_OCIdleState_Set)
1560 01cc 7b09 ld a,(OFST+8,sp)
1561 01ce a101 cp a,#1
1562 01d0 2606 jrne L156
1563 ; 709 TIM2->OISR |= TIM_OISR_OIS2;
1565 01d2 72145266 bset 21094,#2
1567 01d6 2004 jra L356
1568 01d8 L156:
1569 ; 713 TIM2->OISR &= (uint8_t)(~TIM_OISR_OIS2);
1571 01d8 72155266 bres 21094,#2
1572 01dc L356:
1573 ; 717 TIM2->CCR2H = (uint8_t)(TIM2_Pulse >> 8);
1575 01dc 7b06 ld a,(OFST+5,sp)
1576 01de c75263 ld 21091,a
1577 ; 718 TIM2->CCR2L = (uint8_t)(TIM2_Pulse);
1579 01e1 7b07 ld a,(OFST+6,sp)
1580 01e3 c75264 ld 21092,a
1581 ; 719 }
1584 01e6 5b03 addw sp,#3
1585 01e8 81 ret
1783 ; 748 void TIM2_BKRConfig(TIM2_OSSIState_TypeDef TIM2_OSSIState,
1783 ; 749 TIM2_LockLevel_TypeDef TIM2_LockLevel,
1783 ; 750 TIM2_BreakState_TypeDef TIM2_BreakState,
1783 ; 751 TIM2_BreakPolarity_TypeDef TIM2_BreakPolarity,
1783 ; 752 TIM2_AutomaticOutput_TypeDef TIM2_AutomaticOutput)
1783 ; 753
1783 ; 754 {
1784 switch .text
1785 01e9 _TIM2_BKRConfig:
1787 01e9 89 pushw x
1788 01ea 88 push a
1789 00000001 OFST: set 1
1792 ; 756 assert_param(IS_TIM2_OSSI_STATE(TIM2_OSSIState));
1794 ; 757 assert_param(IS_TIM2_LOCK_LEVEL(TIM2_LockLevel));
1796 ; 758 assert_param(IS_TIM2_BREAK_STATE(TIM2_BreakState));
1798 ; 759 assert_param(IS_TIM2_BREAK_POLARITY(TIM2_BreakPolarity));
1800 ; 760 assert_param(IS_TIM2_AUTOMATIC_OUTPUT_STATE(TIM2_AutomaticOutput));
1802 ; 766 TIM2->BKR = (uint8_t)((uint8_t)((uint8_t)((uint8_t)((uint8_t)TIM2_OSSIState | (uint8_t)TIM2_LockLevel) | \
1802 ; 767 (uint8_t)((uint8_t)TIM2_BreakState | (uint8_t)TIM2_BreakPolarity)) | \
1802 ; 768 TIM2_AutomaticOutput));
1804 01eb 7b06 ld a,(OFST+5,sp)
1805 01ed 1a07 or a,(OFST+6,sp)
1806 01ef 6b01 ld (OFST+0,sp),a
1807 01f1 9f ld a,xl
1808 01f2 1a02 or a,(OFST+1,sp)
1809 01f4 1a01 or a,(OFST+0,sp)
1810 01f6 1a08 or a,(OFST+7,sp)
1811 01f8 c75265 ld 21093,a
1812 ; 769 }
1815 01fb 5b03 addw sp,#3
1816 01fd 81 ret
1852 ; 777 void TIM2_CtrlPWMOutputs(FunctionalState NewState)
1852 ; 778 {
1853 switch .text
1854 01fe _TIM2_CtrlPWMOutputs:
1858 ; 780 assert_param(IS_FUNCTIONAL_STATE(NewState));
1860 ; 784 if (NewState != DISABLE)
1862 01fe 4d tnz a
1863 01ff 2706 jreq L5001
1864 ; 786 TIM2->BKR |= TIM_BKR_MOE ;
1866 0201 721e5265 bset 21093,#7
1868 0205 2004 jra L7001
1869 0207 L5001:
1870 ; 790 TIM2->BKR &= (uint8_t)(~TIM_BKR_MOE) ;
1872 0207 721f5265 bres 21093,#7
1873 020b L7001:
1874 ; 792 }
1877 020b 81 ret
1942 ; 812 void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel,
1942 ; 813 TIM2_OCMode_TypeDef TIM2_OCMode)
1942 ; 814 {
1943 switch .text
1944 020c _TIM2_SelectOCxM:
1946 020c 89 pushw x
1947 00000000 OFST: set 0
1950 ; 816 assert_param(IS_TIM2_CHANNEL(TIM2_Channel));
1952 ; 817 assert_param(IS_TIM2_OCM(TIM2_OCMode));
1954 ; 819 if (TIM2_Channel == TIM2_Channel_1)
1956 020d 9e ld a,xh
1957 020e 4d tnz a
1958 020f 2615 jrne L3401
1959 ; 822 TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
1961 0211 7211525b bres 21083,#0
1962 ; 825 TIM2->CCMR1 &= (uint8_t)(~TIM_CCMR_OCM);
1964 0215 c65259 ld a,21081
1965 0218 a48f and a,#143
1966 021a c75259 ld 21081,a
1967 ; 828 TIM2->CCMR1 |= (uint8_t)TIM2_OCMode;
1969 021d 9f ld a,xl
1970 021e ca5259 or a,21081
1971 0221 c75259 ld 21081,a
1973 0224 2014 jra L5401
1974 0226 L3401:
1975 ; 833 TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
1977 0226 7219525b bres 21083,#4
1978 ; 836 TIM2->CCMR2 &= (uint8_t)(~TIM_CCMR_OCM);
1980 022a c6525a ld a,21082
1981 022d a48f and a,#143
1982 022f c7525a ld 21082,a
1983 ; 839 TIM2->CCMR2 |= (uint8_t)TIM2_OCMode;
1985 0232 c6525a ld a,21082
1986 0235 1a02 or a,(OFST+2,sp)
1987 0237 c7525a ld 21082,a
1988 023a L5401:
1989 ; 841 }
1992 023a 85 popw x
1993 023b 81 ret
2027 ; 849 void TIM2_SetCompare1(uint16_t Compare)
2027 ; 850 {
2028 switch .text
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