📄 stm8l15x_tim2.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
43 ; 162 void TIM2_DeInit(void)
43 ; 163 {
45 switch .text
46 0000 _TIM2_DeInit:
50 ; 164 TIM2->CR1 = TIM_CR1_RESET_VALUE;
52 0000 725f5250 clr 21072
53 ; 165 TIM2->CR2 = TIM_CR2_RESET_VALUE;
55 0004 725f5251 clr 21073
56 ; 166 TIM2->SMCR = TIM_SMCR_RESET_VALUE;
58 0008 725f5252 clr 21074
59 ; 167 TIM2->ETR = TIM_ETR_RESET_VALUE;
61 000c 725f5253 clr 21075
62 ; 168 TIM2->IER = TIM_IER_RESET_VALUE;
64 0010 725f5255 clr 21077
65 ; 169 TIM2->SR2 = TIM_SR2_RESET_VALUE;
67 0014 725f5257 clr 21079
68 ; 172 TIM2->CCER1 = TIM_CCER1_RESET_VALUE;
70 0018 725f525b clr 21083
71 ; 174 TIM2->CCMR1 = 0x01;/*TIM2_ICxSource_TIxFPx */
73 001c 35015259 mov 21081,#1
74 ; 175 TIM2->CCMR2 = 0x01;/*TIM2_ICxSource_TIxFPx */
76 0020 3501525a mov 21082,#1
77 ; 178 TIM2->CCER1 = TIM_CCER1_RESET_VALUE;
79 0024 725f525b clr 21083
80 ; 179 TIM2->CCMR1 = TIM_CCMR1_RESET_VALUE;
82 0028 725f5259 clr 21081
83 ; 180 TIM2->CCMR2 = TIM_CCMR2_RESET_VALUE;
85 002c 725f525a clr 21082
86 ; 182 TIM2->CNTRH = TIM_CNTRH_RESET_VALUE;
88 0030 725f525c clr 21084
89 ; 183 TIM2->CNTRL = TIM_CNTRL_RESET_VALUE;
91 0034 725f525d clr 21085
92 ; 185 TIM2->PSCR = TIM_PSCR_RESET_VALUE;
94 0038 725f525e clr 21086
95 ; 187 TIM2->ARRH = TIM_ARRH_RESET_VALUE;
97 003c 35ff525f mov 21087,#255
98 ; 188 TIM2->ARRL = TIM_ARRL_RESET_VALUE;
100 0040 35ff5260 mov 21088,#255
101 ; 190 TIM2->CCR1H = TIM_CCR1H_RESET_VALUE;
103 0044 725f5261 clr 21089
104 ; 191 TIM2->CCR1L = TIM_CCR1L_RESET_VALUE;
106 0048 725f5262 clr 21090
107 ; 192 TIM2->CCR2H = TIM_CCR2H_RESET_VALUE;
109 004c 725f5263 clr 21091
110 ; 193 TIM2->CCR2L = TIM_CCR2L_RESET_VALUE;
112 0050 725f5264 clr 21092
113 ; 196 TIM2->OISR = TIM_OISR_RESET_VALUE;
115 0054 725f5266 clr 21094
116 ; 197 TIM2->EGR = 0x01;/* TIM_EGR_UG */
118 0058 35015258 mov 21080,#1
119 ; 198 TIM2->BKR = TIM_BKR_RESET_VALUE;
121 005c 725f5265 clr 21093
122 ; 199 TIM2->SR1 = TIM_SR1_RESET_VALUE;
124 0060 725f5256 clr 21078
125 ; 200 }
128 0064 81 ret
290 ; 225 void TIM2_TimeBaseInit(TIM2_Prescaler_TypeDef TIM2_Prescaler,
290 ; 226 TIM2_CounterMode_TypeDef TIM2_CounterMode,
290 ; 227 uint16_t TIM2_Period)
290 ; 228 {
291 switch .text
292 0065 _TIM2_TimeBaseInit:
294 0065 89 pushw x
295 00000000 OFST: set 0
298 ; 230 assert_param(IS_TIM2_PRESCALER(TIM2_Prescaler));
300 ; 231 assert_param(IS_TIM2_COUNTER_MODE(TIM2_CounterMode));
302 ; 236 TIM2->ARRH = (uint8_t)(TIM2_Period >> 8) ;
304 0066 7b05 ld a,(OFST+5,sp)
305 0068 c7525f ld 21087,a
306 ; 237 TIM2->ARRL = (uint8_t)(TIM2_Period);
308 006b 7b06 ld a,(OFST+6,sp)
309 006d c75260 ld 21088,a
310 ; 240 TIM2->PSCR = (uint8_t)(TIM2_Prescaler);
312 0070 9e ld a,xh
313 0071 c7525e ld 21086,a
314 ; 243 TIM2->CR1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS)) & ((uint8_t)(~TIM_CR1_DIR));
316 0074 c65250 ld a,21072
317 0077 a48f and a,#143
318 0079 c75250 ld 21072,a
319 ; 244 TIM2->CR1 |= (uint8_t)(TIM2_CounterMode);
321 007c 9f ld a,xl
322 007d ca5250 or a,21072
323 0080 c75250 ld 21072,a
324 ; 247 TIM2->EGR = TIM2_EventSource_Update;
326 0083 35015258 mov 21080,#1
327 ; 248 }
330 0087 85 popw x
331 0088 81 ret
399 ; 268 void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
399 ; 269 TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
399 ; 270 {
400 switch .text
401 0089 _TIM2_PrescalerConfig:
405 ; 272 assert_param(IS_TIM2_PRESCALER(Prescaler));
407 ; 273 assert_param(IS_TIM2_PRESCALER_RELOAD(TIM2_PSCReloadMode));
409 ; 276 TIM2->PSCR = (uint8_t)(Prescaler);
411 0089 9e ld a,xh
412 008a c7525e ld 21086,a
413 ; 279 if (TIM2_PSCReloadMode == TIM2_PSCReloadMode_Immediate)
415 008d 9f ld a,xl
416 008e a101 cp a,#1
417 0090 2606 jrne L741
418 ; 281 TIM2->EGR |= TIM_EGR_UG ;
420 0092 72105258 bset 21080,#0
422 0096 2004 jra L151
423 0098 L741:
424 ; 285 TIM2->EGR &= (uint8_t)(~TIM_EGR_UG) ;
426 0098 72115258 bres 21080,#0
427 009c L151:
428 ; 287 }
431 009c 81 ret
476 ; 300 void TIM2_CounterModeConfig(TIM2_CounterMode_TypeDef TIM2_CounterMode)
476 ; 301 {
477 switch .text
478 009d _TIM2_CounterModeConfig:
480 009d 88 push a
481 009e 88 push a
482 00000001 OFST: set 1
485 ; 302 uint8_t tmpcr1 = 0;
487 ; 305 assert_param(IS_TIM2_COUNTER_MODE(TIM2_CounterMode));
489 ; 307 tmpcr1 = TIM2->CR1;
491 009f c65250 ld a,21072
492 00a2 6b01 ld (OFST+0,sp),a
493 ; 310 tmpcr1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS) & (uint8_t)(~TIM_CR1_DIR));
495 00a4 7b01 ld a,(OFST+0,sp)
496 00a6 a48f and a,#143
497 00a8 6b01 ld (OFST+0,sp),a
498 ; 313 tmpcr1 |= (uint8_t)TIM2_CounterMode;
500 00aa 7b01 ld a,(OFST+0,sp)
501 00ac 1a02 or a,(OFST+1,sp)
502 00ae 6b01 ld (OFST+0,sp),a
503 ; 315 TIM2->CR1 = tmpcr1;
505 00b0 7b01 ld a,(OFST+0,sp)
506 00b2 c75250 ld 21072,a
507 ; 316 }
510 00b5 85 popw x
511 00b6 81 ret
545 ; 324 void TIM2_SetCounter(uint16_t Counter)
545 ; 325 {
546 switch .text
547 00b7 _TIM2_SetCounter:
551 ; 328 TIM2->CNTRH = (uint8_t)(Counter >> 8);
553 00b7 9e ld a,xh
554 00b8 c7525c ld 21084,a
555 ; 329 TIM2->CNTRL = (uint8_t)(Counter);
557 00bb 9f ld a,xl
558 00bc c7525d ld 21085,a
559 ; 330 }
562 00bf 81 ret
596 ; 338 void TIM2_SetAutoreload(uint16_t Autoreload)
596 ; 339 {
597 switch .text
598 00c0 _TIM2_SetAutoreload:
602 ; 341 TIM2->ARRH = (uint8_t)(Autoreload >> 8);
604 00c0 9e ld a,xh
605 00c1 c7525f ld 21087,a
606 ; 342 TIM2->ARRL = (uint8_t)(Autoreload);
608 00c4 9f ld a,xl
609 00c5 c75260 ld 21088,a
610 ; 343 }
613 00c8 81 ret
665 ; 350 uint16_t TIM2_GetCounter(void)
665 ; 351 {
666 switch .text
667 00c9 _TIM2_GetCounter:
669 00c9 5204 subw sp,#4
670 00000004 OFST: set 4
673 ; 352 uint16_t tmpcnt = 0;
675 ; 355 tmpcntrh = TIM2->CNTRH;
677 00cb c6525c ld a,21084
678 00ce 6b02 ld (OFST-2,sp),a
679 ; 356 tmpcntrl = TIM2->CNTRL;
681 00d0 c6525d ld a,21085
682 00d3 6b01 ld (OFST-3,sp),a
683 ; 358 tmpcnt = (uint16_t)(tmpcntrl);
685 00d5 7b01 ld a,(OFST-3,sp)
686 00d7 5f clrw x
687 00d8 97 ld xl,a
688 00d9 1f03 ldw (OFST-1,sp),x
689 ; 359 tmpcnt |= (uint16_t)((uint16_t)tmpcntrh << 8);
691 00db 7b02 ld a,(OFST-2,sp)
692 00dd 5f clrw x
693 00de 97 ld xl,a
694 00df 4f clr a
695 00e0 02 rlwa x,a
696 00e1 01 rrwa x,a
697 00e2 1a04 or a,(OFST+0,sp)
698 00e4 01 rrwa x,a
699 00e5 1a03 or a,(OFST-1,sp)
700 00e7 01 rrwa x,a
701 00e8 1f03 ldw (OFST-1,sp),x
702 ; 361 return ((uint16_t)tmpcnt);
704 00ea 1e03 ldw x,(OFST-1,sp)
707 00ec 5b04 addw sp,#4
708 00ee 81 ret
732 ; 377 TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void)
732 ; 378 {
733 switch .text
734 00ef _TIM2_GetPrescaler:
738 ; 380 return ((TIM2_Prescaler_TypeDef)TIM2->PSCR);
740 00ef c6525e ld a,21086
743 00f2 81 ret
799 ; 390 void TIM2_UpdateDisableConfig(FunctionalState NewState)
799 ; 391 {
800 switch .text
801 00f3 _TIM2_UpdateDisableConfig:
805 ; 393 assert_param(IS_FUNCTIONAL_STATE(NewState));
807 ; 396 if (NewState != DISABLE)
809 00f3 4d tnz a
810 00f4 2706 jreq L513
811 ; 398 TIM2->CR1 |= TIM_CR1_UDIS;
813 00f6 72125250 bset 21072,#1
815 00fa 2004 jra L713
816 00fc L513:
817 ; 402 TIM2->CR1 &= (uint8_t)(~TIM_CR1_UDIS);
819 00fc 72135250 bres 21072,#1
820 0100 L713:
821 ; 404 }
824 0100 81 ret
882 ; 414 void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
882 ; 415 {
883 switch .text
884 0101 _TIM2_UpdateRequestConfig:
888 ; 417 assert_param(IS_TIM2_UPDATE_SOURCE(TIM2_UpdateSource));
890 ; 420 if (TIM2_UpdateSource == TIM2_UpdateSource_Regular)
892 0101 a101 cp a,#1
893 0103 2606 jrne L743
894 ; 422 TIM2->CR1 |= TIM_CR1_URS ;
896 0105 72145250 bset 21072,#2
898 0109 2004 jra L153
899 010b L743:
900 ; 426 TIM2->CR1 &= (uint8_t)(~TIM_CR1_URS);
902 010b 72155250 bres 21072,#2
903 010f L153:
904 ; 428 }
907 010f 81 ret
943 ; 436 void TIM2_ARRPreloadConfig(FunctionalState NewState)
943 ; 437 {
944 switch .text
945 0110 _TIM2_ARRPreloadConfig:
949 ; 439 assert_param(IS_FUNCTIONAL_STATE(NewState));
951 ; 442 if (NewState != DISABLE)
953 0110 4d tnz a
954 0111 2706 jreq L173
955 ; 444 TIM2->CR1 |= TIM_CR1_ARPE;
957 0113 721e5250 bset 21072,#7
959 0117 2004 jra L373
960 0119 L173:
961 ; 448 TIM2->CR1 &= (uint8_t)(~TIM_CR1_ARPE);
963 0119 721f5250 bres 21072,#7
964 011d L373:
965 ; 450 }
968 011d 81 ret
1025 ; 460 void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode)
1025 ; 461 {
1026 switch .text
1027 011e _TIM2_SelectOnePulseMode:
1031 ; 463 assert_param(IS_TIM2_OPM_MODE(TIM2_OPMode));
1033 ; 466 if (TIM2_OPMode == TIM2_OPMode_Single)
1035 011e a101 cp a,#1
1036 0120 2606 jrne L324
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