📄 stm8l15x_itc.ls
字号:
704 switch .const
705 003a L44:
706 003a 00e2 dc.w L722
707 003c 00e2 dc.w L722
708 003e 00e2 dc.w L722
709 0040 00f4 dc.w L132
710 0042 00f4 dc.w L132
711 0044 00f4 dc.w L132
712 0046 00f4 dc.w L132
713 0048 0106 dc.w L332
714 004a 0106 dc.w L332
715 004c 0106 dc.w L332
716 004e 0106 dc.w L332
717 0050 0118 dc.w L532
718 0052 0118 dc.w L532
719 0054 0118 dc.w L532
720 0056 0118 dc.w L532
721 0058 012a dc.w L732
722 005a 012a dc.w L732
723 005c 012a dc.w L732
724 005e 012a dc.w L732
725 0060 013c dc.w L142
726 0062 013c dc.w L142
727 0064 013c dc.w L142
728 0066 013c dc.w L142
729 0068 014e dc.w L342
730 006a 014e dc.w L342
731 006c 014e dc.w L342
732 006e 014e dc.w L342
733 0070 0160 dc.w L542
734 0072 0160 dc.w L542
735 ; 241 void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel)
735 ; 242 {
736 switch .text
737 00aa _ITC_SetSoftwarePriority:
739 00aa 89 pushw x
740 00ab 89 pushw x
741 00000002 OFST: set 2
744 ; 243 uint8_t Mask = 0;
746 ; 244 uint8_t NewPriority = 0;
748 ; 247 assert_param(IS_ITC_IRQ(IRQn));
750 ; 248 assert_param(IS_ITC_PRIORITY(ITC_PriorityLevel));
752 ; 251 assert_param(IS_ITC_INTERRUPTS_DISABLED);
754 ; 255 Mask = (uint8_t)(~(uint8_t)(0x03U << ((IRQn % 4U) * 2U)));
756 00ac 9e ld a,xh
757 00ad a403 and a,#3
758 00af 48 sll a
759 00b0 5f clrw x
760 00b1 97 ld xl,a
761 00b2 a603 ld a,#3
762 00b4 5d tnzw x
763 00b5 2704 jreq L23
764 00b7 L43:
765 00b7 48 sll a
766 00b8 5a decw x
767 00b9 26fc jrne L43
768 00bb L23:
769 00bb 43 cpl a
770 00bc 6b01 ld (OFST-1,sp),a
771 ; 257 NewPriority = (uint8_t)((uint8_t)(ITC_PriorityLevel) << ((IRQn % 4U) * 2U));
773 00be 7b03 ld a,(OFST+1,sp)
774 00c0 a403 and a,#3
775 00c2 48 sll a
776 00c3 5f clrw x
777 00c4 97 ld xl,a
778 00c5 7b04 ld a,(OFST+2,sp)
779 00c7 5d tnzw x
780 00c8 2704 jreq L63
781 00ca L04:
782 00ca 48 sll a
783 00cb 5a decw x
784 00cc 26fc jrne L04
785 00ce L63:
786 00ce 6b02 ld (OFST+0,sp),a
787 ; 259 switch (IRQn)
789 00d0 7b03 ld a,(OFST+1,sp)
791 ; 360 default:
791 ; 361 break;
792 00d2 4a dec a
793 00d3 a11d cp a,#29
794 00d5 2407 jruge L24
795 00d7 5f clrw x
796 00d8 97 ld xl,a
797 00d9 58 sllw x
798 00da de003a ldw x,(L44,x)
799 00dd fc jp (x)
800 00de L24:
801 00de ac700170 jpf L503
802 00e2 L722:
803 ; 261 case FLASH_IRQn:
803 ; 262 case DMA1_CHANNEL0_1_IRQn:
803 ; 263 case DMA1_CHANNEL2_3_IRQn:
803 ; 264 ITC->ISPR1 &= Mask;
805 00e2 c67f70 ld a,32624
806 00e5 1401 and a,(OFST-1,sp)
807 00e7 c77f70 ld 32624,a
808 ; 265 ITC->ISPR1 |= NewPriority;
810 00ea c67f70 ld a,32624
811 00ed 1a02 or a,(OFST+0,sp)
812 00ef c77f70 ld 32624,a
813 ; 266 break;
815 00f2 207c jra L503
816 00f4 L132:
817 ; 268 case EXTIE_F_PVD_IRQn:
817 ; 269 #ifdef STM8L15X_MD
817 ; 270 case RTC_IRQn:
817 ; 271 case EXTIB_IRQn:
817 ; 272 case EXTID_IRQn:
817 ; 273 #elif defined (STM8L15X_LD)
817 ; 274 case RTC_CSSLSE_IRQn:
817 ; 275 case EXTIB_IRQn:
817 ; 276 case EXTID_IRQn:
817 ; 277 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
817 ; 278 case RTC_CSSLSE_IRQn:
817 ; 279 case EXTIB_G_IRQn:
817 ; 280 case EXTID_H_IRQn:
817 ; 281 #endif /* STM8L15X_MD */
817 ; 282 ITC->ISPR2 &= Mask;
819 00f4 c67f71 ld a,32625
820 00f7 1401 and a,(OFST-1,sp)
821 00f9 c77f71 ld 32625,a
822 ; 283 ITC->ISPR2 |= NewPriority;
824 00fc c67f71 ld a,32625
825 00ff 1a02 or a,(OFST+0,sp)
826 0101 c77f71 ld 32625,a
827 ; 284 break;
829 0104 206a jra L503
830 0106 L332:
831 ; 286 case EXTI0_IRQn:
831 ; 287 case EXTI1_IRQn:
831 ; 288 case EXTI2_IRQn:
831 ; 289 case EXTI3_IRQn:
831 ; 290 ITC->ISPR3 &= Mask;
833 0106 c67f72 ld a,32626
834 0109 1401 and a,(OFST-1,sp)
835 010b c77f72 ld 32626,a
836 ; 291 ITC->ISPR3 |= NewPriority;
838 010e c67f72 ld a,32626
839 0111 1a02 or a,(OFST+0,sp)
840 0113 c77f72 ld 32626,a
841 ; 292 break;
843 0116 2058 jra L503
844 0118 L532:
845 ; 294 case EXTI4_IRQn:
845 ; 295 case EXTI5_IRQn:
845 ; 296 case EXTI6_IRQn:
845 ; 297 case EXTI7_IRQn:
845 ; 298 ITC->ISPR4 &= Mask;
847 0118 c67f73 ld a,32627
848 011b 1401 and a,(OFST-1,sp)
849 011d c77f73 ld 32627,a
850 ; 299 ITC->ISPR4 |= NewPriority;
852 0120 c67f73 ld a,32627
853 0123 1a02 or a,(OFST+0,sp)
854 0125 c77f73 ld 32627,a
855 ; 300 break;
857 0128 2046 jra L503
858 012a L732:
859 ; 302 case SWITCH_CSS_BREAK_DAC_IRQn:
859 ; 303 #else
859 ; 304 case SWITCH_CSS_IRQn:
859 ; 305 #endif /* STM8L15X_LD */
859 ; 306 case ADC1_COMP_IRQn:
859 ; 307 #ifdef STM8L15X_MD
859 ; 308 case LCD_IRQn:
859 ; 309 case TIM2_UPD_OVF_TRG_BRK_IRQn:
859 ; 310 #elif defined (STM8L15X_LD)
859 ; 311 case TIM2_UPD_OVF_TRG_BRK_IRQn:
859 ; 312 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
859 ; 313 case LCD_AES_IRQn:
859 ; 314 case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
859 ; 315 #endif /* STM8L15X_MD */
859 ; 316 ITC->ISPR5 &= Mask;
861 012a c67f74 ld a,32628
862 012d 1401 and a,(OFST-1,sp)
863 012f c77f74 ld 32628,a
864 ; 317 ITC->ISPR5 |= NewPriority;
866 0132 c67f74 ld a,32628
867 0135 1a02 or a,(OFST+0,sp)
868 0137 c77f74 ld 32628,a
869 ; 318 break;
871 013a 2034 jra L503
872 013c L142:
873 ; 320 case TIM1_UPD_OVF_TRG_IRQn:
873 ; 321 #endif /* STM8L15X_LD */
873 ; 322 #if defined (STM8L15X_MD) || defined (STM8L15X_LD)
873 ; 323 case TIM2_CC_IRQn:
873 ; 324 case TIM3_UPD_OVF_TRG_BRK_IRQn :
873 ; 325 case TIM3_CC_IRQn:
873 ; 326 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
873 ; 327 case TIM2_CC_USART2_RX_IRQn:
873 ; 328 case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
873 ; 329 case TIM3_CC_USART3_RX_IRQn:
873 ; 330 #endif /* STM8L15X_MD */
873 ; 331 ITC->ISPR6 &= Mask;
875 013c c67f75 ld a,32629
876 013f 1401 and a,(OFST-1,sp)
877 0141 c77f75 ld 32629,a
878 ; 332 ITC->ISPR6 |= NewPriority;
880 0144 c67f75 ld a,32629
881 0147 1a02 or a,(OFST+0,sp)
882 0149 c77f75 ld 32629,a
883 ; 333 break;
885 014c 2022 jra L503
886 014e L342:
887 ; 336 case TIM1_CC_IRQn:
887 ; 337 #endif /* STM8L15X_LD */
887 ; 338 case TIM4_UPD_OVF_TRG_IRQn:
887 ; 339 case SPI1_IRQn:
887 ; 340 #if defined (STM8L15X_MD) || defined (STM8L15X_LD)
887 ; 341 case USART1_TX_IRQn:
887 ; 342 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
887 ; 343 case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
887 ; 344 #endif /* STM8L15X_MD */
887 ; 345 ITC->ISPR7 &= Mask;
889 014e c67f76 ld a,32630
890 0151 1401 and a,(OFST-1,sp)
891 0153 c77f76 ld 32630,a
892 ; 346 ITC->ISPR7 |= NewPriority;
894 0156 c67f76 ld a,32630
895 0159 1a02 or a,(OFST+0,sp)
896 015b c77f76 ld 32630,a
897 ; 347 break;
899 015e 2010 jra L503
900 0160 L542:
901 ; 350 case USART1_RX_IRQn:
901 ; 351 case I2C1_IRQn:
901 ; 352 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
901 ; 353 case USART1_RX_TIM5_CC_IRQn:
901 ; 354 case I2C1_SPI2_IRQn:
901 ; 355 #endif /* STM8L15X_MD */
901 ; 356 ITC->ISPR8 &= Mask;
903 0160 c67f77 ld a,32631
904 0163 1401 and a,(OFST-1,sp)
905 0165 c77f77 ld 32631,a
906 ; 357 ITC->ISPR8 |= NewPriority;
908 0168 c67f77 ld a,32631
909 016b 1a02 or a,(OFST+0,sp)
910 016d c77f77 ld 32631,a
911 ; 358 break;
913 0170 L742:
914 ; 360 default:
914 ; 361 break;
916 0170 L503:
917 ; 363 }
920 0170 5b04 addw sp,#4
921 0172 81 ret
934 xdef _ITC_GetSoftwarePriority
935 xdef _ITC_SetSoftwarePriority
936 xdef _ITC_GetSoftIntStatus
937 xdef _ITC_GetCPUCC
938 xdef _ITC_DeInit
957 end
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