📄 stm8l15x_itc.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.10 - 10 Feb 2011
3 ; Generator (Limited) V4.3.6 - 15 Feb 2011
43 ; 50 uint8_t ITC_GetCPUCC(void)
43 ; 51 {
45 switch .text
46 0000 _ITC_GetCPUCC:
50 ; 53 _asm("push cc");
53 0000 8a push cc
55 ; 54 _asm("pop a");
58 0001 84 pop a
60 ; 55 return; /* Ignore compiler warning, the returned value is in A register */
63 0002 81 ret
86 ; 81 void ITC_DeInit(void)
86 ; 82 {
87 switch .text
88 0003 _ITC_DeInit:
92 ; 83 ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
94 0003 35ff7f70 mov 32624,#255
95 ; 84 ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
97 0007 35ff7f71 mov 32625,#255
98 ; 85 ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
100 000b 35ff7f72 mov 32626,#255
101 ; 86 ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
103 000f 35ff7f73 mov 32627,#255
104 ; 87 ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
106 0013 35ff7f74 mov 32628,#255
107 ; 88 ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
109 0017 35ff7f75 mov 32629,#255
110 ; 89 ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
112 001b 35ff7f76 mov 32630,#255
113 ; 90 ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
115 001f 35ff7f77 mov 32631,#255
116 ; 91 }
119 0023 81 ret
144 ; 98 uint8_t ITC_GetSoftIntStatus(void)
144 ; 99 {
145 switch .text
146 0024 _ITC_GetSoftIntStatus:
150 ; 100 return ((uint8_t)(ITC_GetCPUCC() & CPU_SOFT_INT_DISABLED));
152 0024 adda call _ITC_GetCPUCC
154 0026 a428 and a,#40
157 0028 81 ret
466 .const: section .text
467 0000 L22:
468 0000 004d dc.w L14
469 0002 004d dc.w L14
470 0004 004d dc.w L14
471 0006 0056 dc.w L34
472 0008 0056 dc.w L34
473 000a 0056 dc.w L34
474 000c 0056 dc.w L34
475 000e 005f dc.w L54
476 0010 005f dc.w L54
477 0012 005f dc.w L54
478 0014 005f dc.w L54
479 0016 0068 dc.w L74
480 0018 0068 dc.w L74
481 001a 0068 dc.w L74
482 001c 0068 dc.w L74
483 001e 0071 dc.w L15
484 0020 0071 dc.w L15
485 0022 0071 dc.w L15
486 0024 0071 dc.w L15
487 0026 007a dc.w L35
488 0028 007a dc.w L35
489 002a 007a dc.w L35
490 002c 007a dc.w L35
491 002e 0083 dc.w L55
492 0030 0083 dc.w L55
493 0032 0083 dc.w L55
494 0034 0083 dc.w L55
495 0036 008c dc.w L75
496 0038 008c dc.w L75
497 ; 108 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn)
497 ; 109 {
498 switch .text
499 0029 _ITC_GetSoftwarePriority:
501 0029 88 push a
502 002a 89 pushw x
503 00000002 OFST: set 2
506 ; 110 uint8_t Value = 0;
508 002b 0f02 clr (OFST+0,sp)
509 ; 111 uint8_t Mask = 0;
511 ; 114 assert_param(IS_ITC_IRQ(IRQn));
513 ; 117 Mask = (uint8_t)(0x03U << ((IRQn % 4U) * 2U));
515 002d a403 and a,#3
516 002f 48 sll a
517 0030 5f clrw x
518 0031 97 ld xl,a
519 0032 a603 ld a,#3
520 0034 5d tnzw x
521 0035 2704 jreq L41
522 0037 L61:
523 0037 48 sll a
524 0038 5a decw x
525 0039 26fc jrne L61
526 003b L41:
527 003b 6b01 ld (OFST-1,sp),a
528 ; 119 switch (IRQn)
530 003d 7b03 ld a,(OFST+1,sp)
532 ; 214 default:
532 ; 215 break;
533 003f 4a dec a
534 0040 a11d cp a,#29
535 0042 2407 jruge L02
536 0044 5f clrw x
537 0045 97 ld xl,a
538 0046 58 sllw x
539 0047 de0000 ldw x,(L22,x)
540 004a fc jp (x)
541 004b L02:
542 004b 2046 jra L522
543 004d L14:
544 ; 121 case FLASH_IRQn:
544 ; 122 case DMA1_CHANNEL0_1_IRQn:
544 ; 123 case DMA1_CHANNEL2_3_IRQn:
544 ; 124 Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */
546 004d c67f70 ld a,32624
547 0050 1401 and a,(OFST-1,sp)
548 0052 6b02 ld (OFST+0,sp),a
549 ; 125 break;
551 0054 203d jra L522
552 0056 L34:
553 ; 127 case EXTIE_F_PVD_IRQn:
553 ; 128 #ifdef STM8L15X_MD
553 ; 129 case RTC_IRQn:
553 ; 130 case EXTIB_IRQn:
553 ; 131 case EXTID_IRQn:
553 ; 132 #elif defined (STM8L15X_LD)
553 ; 133 case RTC_CSSLSE_IRQn:
553 ; 134 case EXTIB_IRQn:
553 ; 135 case EXTID_IRQn:
553 ; 136 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
553 ; 137 case RTC_CSSLSE_IRQn:
553 ; 138 case EXTIB_G_IRQn:
553 ; 139 case EXTID_H_IRQn:
553 ; 140 #endif /* STM8L15X_MD */
553 ; 141 Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */
555 0056 c67f71 ld a,32625
556 0059 1401 and a,(OFST-1,sp)
557 005b 6b02 ld (OFST+0,sp),a
558 ; 142 break;
560 005d 2034 jra L522
561 005f L54:
562 ; 144 case EXTI0_IRQn:
562 ; 145 case EXTI1_IRQn:
562 ; 146 case EXTI2_IRQn:
562 ; 147 case EXTI3_IRQn:
562 ; 148 Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */
564 005f c67f72 ld a,32626
565 0062 1401 and a,(OFST-1,sp)
566 0064 6b02 ld (OFST+0,sp),a
567 ; 149 break;
569 0066 202b jra L522
570 0068 L74:
571 ; 151 case EXTI4_IRQn:
571 ; 152 case EXTI5_IRQn:
571 ; 153 case EXTI6_IRQn:
571 ; 154 case EXTI7_IRQn:
571 ; 155 Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */
573 0068 c67f73 ld a,32627
574 006b 1401 and a,(OFST-1,sp)
575 006d 6b02 ld (OFST+0,sp),a
576 ; 156 break;
578 006f 2022 jra L522
579 0071 L15:
580 ; 161 case SWITCH_CSS_BREAK_DAC_IRQn:
580 ; 162 #endif /* STM8L15X_LD */
580 ; 163 case ADC1_COMP_IRQn:
580 ; 164 #ifdef STM8L15X_MD
580 ; 165 case LCD_IRQn:
580 ; 166 case TIM2_UPD_OVF_TRG_BRK_IRQn:
580 ; 167 #elif defined (STM8L15X_LD)
580 ; 168 case TIM2_UPD_OVF_TRG_BRK_IRQn:
580 ; 169 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
580 ; 170 case LCD_AES_IRQn:
580 ; 171 case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
580 ; 172 #endif /* STM8L15X_MD */
580 ; 173 Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */
582 0071 c67f74 ld a,32628
583 0074 1401 and a,(OFST-1,sp)
584 0076 6b02 ld (OFST+0,sp),a
585 ; 174 break;
587 0078 2019 jra L522
588 007a L35:
589 ; 177 case TIM1_UPD_OVF_TRG_IRQn:
589 ; 178 #endif /* STM8L15X_LD */
589 ; 179 #if defined (STM8L15X_MD) || defined (STM8L15X_LD)
589 ; 180 case TIM2_CC_IRQn:
589 ; 181 case TIM3_UPD_OVF_TRG_BRK_IRQn :
589 ; 182 case TIM3_CC_IRQn:
589 ; 183 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
589 ; 184 case TIM2_CC_USART2_RX_IRQn:
589 ; 185 case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
589 ; 186 case TIM3_CC_USART3_RX_IRQn:
589 ; 187 #endif /* STM8L15X_MD */
589 ; 188 Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */
591 007a c67f75 ld a,32629
592 007d 1401 and a,(OFST-1,sp)
593 007f 6b02 ld (OFST+0,sp),a
594 ; 189 break;
596 0081 2010 jra L522
597 0083 L55:
598 ; 192 case TIM1_CC_IRQn:
598 ; 193 #endif /* STM8L15X_LD */
598 ; 194 case TIM4_UPD_OVF_TRG_IRQn:
598 ; 195 case SPI1_IRQn:
598 ; 196 #if defined (STM8L15X_MD) || defined (STM8L15X_LD)
598 ; 197 case USART1_TX_IRQn:
598 ; 198 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
598 ; 199 case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
598 ; 200 #endif /* STM8L15X_MD || STM8L15X_LD */
598 ; 201 Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */
600 0083 c67f76 ld a,32630
601 0086 1401 and a,(OFST-1,sp)
602 0088 6b02 ld (OFST+0,sp),a
603 ; 202 break;
605 008a 2007 jra L522
606 008c L75:
607 ; 205 case USART1_RX_IRQn:
607 ; 206 case I2C1_IRQn:
607 ; 207 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
607 ; 208 case USART1_RX_TIM5_CC_IRQn:
607 ; 209 case I2C1_SPI2_IRQn:
607 ; 210 #endif /* STM8L15X_MD || STM8L15X_LD*/
607 ; 211 Value = (uint8_t)(ITC->ISPR8 & Mask); /* Read software priority */
609 008c c67f77 ld a,32631
610 008f 1401 and a,(OFST-1,sp)
611 0091 6b02 ld (OFST+0,sp),a
612 ; 212 break;
614 0093 L16:
615 ; 214 default:
615 ; 215 break;
617 0093 L522:
618 ; 218 Value >>= (uint8_t)((IRQn % 4u) * 2u);
620 0093 7b03 ld a,(OFST+1,sp)
621 0095 a403 and a,#3
622 0097 48 sll a
623 0098 5f clrw x
624 0099 97 ld xl,a
625 009a 7b02 ld a,(OFST+0,sp)
626 009c 5d tnzw x
627 009d 2704 jreq L42
628 009f L62:
629 009f 44 srl a
630 00a0 5a decw x
631 00a1 26fc jrne L62
632 00a3 L42:
633 00a3 6b02 ld (OFST+0,sp),a
634 ; 220 return((ITC_PriorityLevel_TypeDef)Value);
636 00a5 7b02 ld a,(OFST+0,sp)
639 00a7 5b03 addw sp,#3
640 00a9 81 ret
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