📄 os_cpu.h
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/*********************************************************************
*File: OS_CPU.H - V2.52 port for C6416
*Author: Jean J. Labrosse
*Data:
*modification history:
* 2006.04.20 rongjie revised contents referring to C6416
*DESCRIPTION:
little endian, C code in relation to processor.
*********************************************************************/
#ifdef OS_CPU_GLOBALS
#define OS_CPU_EXT
#else
#define OS_CPU_EXT extern
#endif
/* DATA TYPES (Compiler Specific) */
typedef unsigned char BOOLEAN;
typedef unsigned char INT8U; /* Unsigned 8 bit quantity */
typedef signed char INT8S; /* Signed 8 bit quantity */
typedef unsigned short INT16U; /* Unsigned 16 bit quantity */
typedef signed short INT16S; /* Signed 16 bit quantity */
typedef unsigned int INT32U; /* Unsigned 32 bit quantity */
typedef signed int INT32S; /* Signed 32 bit quantity */
typedef float FP32; /* Single precision floating point */
typedef double FP64; /* Double precision floating point */
typedef unsigned int OS_STK; /* Each stack entry is 32-bit wide in C6711DSP */
#define BYTE INT8S /* Define data types for backward compatibility ... */
#define UBYTE INT8U /* ... to uC/OS V1.xx. Not actually needed for ... */
#define WORD INT16S /* ... uC/OS-II. */
#define UWORD INT16U
#define LONG INT32S
#define ULONG INT32U
/*
*********************************************************************************************************
* Intel 80x86 (Real-Mode, Large Model)
*
* Method #1: Disable/Enable interrupts using simple instructions. After critical section, interrupts
* will be enabled even if they were disabled before entering the critical section.
*
* Method #2: Disable/Enable interrupts by preserving the state of interrupts. In other words, if
* interrupts were disabled before entering the critical section, they will be disabled when
* leaving the critical section.
*
* Method #3: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you
* would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
* disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to
* disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr'
* into the CPU's status register.
*********************************************************************************************************
*/
#define OS_CRITICAL_METHOD 1
#if OS_CRITICAL_METHOD == 1
extern cregister volatile unsigned int CSR ;
#define OS_ENTER_CRITICAL() CSR &= 0xfffe;//asm(" nop 4"); /* Disable interrupts */
#define OS_EXIT_CRITICAL() CSR |= 0x0001;//asm(" nop 4"); /* Enable interrupts */
#endif
#if OS_CRITICAL_METHOD == 2
#define OS_ENTER_CRITICAL() Disable_int() /* Disable interrupts */
#define OS_EXIT_CRITICAL() Restore_int() /* Enable interrupts */
#endif
#if OS_CRITICAL_METHOD == 3
#define OS_ENTER_CRITICAL() /* Disable interrupts */
#define OS_EXIT_CRITICAL() /* Enable interrupts */
#endif
/* function prototypes */
#if OS_CRITICAL_METHOD == 2
extern void Disable_int(void); /* function for disable interrupt */
extern void Restore_int(void); /* function for restore interrupt */
#endif
extern void ctwSave(void); /* save registers */
extern void ctwRest(void); /* restore registers */
/*
*********************************************************************************************************
* TI C6416 DSP Miscellaneous
*********************************************************************************************************
*/
#define OS_STK_GROWTH 1 /* Stack grows from HIGH to LOW memory */
#define OS_TASK_SW() OSCtxSw()
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