splb30.inc

asm.rar 拉斯维加丝盘源代码 ASM51

;Memory layout
;
;       0000H ┌────────────┐
;             │     I/O & Control      │      16 Bytes
;       001FH ├────────────┤
;             │Ext I/O or  Not used    │
;       0040H ├────────────┤
;             │      SRAM Page 0       │      160 Bytes
;       00FFH ├────────────┤
;             │      Stack Area        │      32  Bytes
;       0200H ├────────────┤
;             │      SRAM Page 1       │      64  Bytes
;       07FFH └────────────┘
;
;
;       2000H ┌────────────┐
;             │                        │
;             │     Ext Ram            │
;             │                        │
;       4000H ├────────────┼───┬───┬───┐
;             │     BANK 0 (LOW)       │BANK 1│BANK 2│BANK 3│
;             │(i.e. In fact, it is    │      │      │      │
;             │      c000 to ffffh)    │      │      │      │
;       8000H ├────────────┤      │      │      │
;             │                        │      │      │      │
;             │     BANK 0 (HIGH)      │      │      │      │
;             │                        │      │      │      │
;       c000H ├────────────┼───┴───┴───┘
;             │                        │
;             │      Common Area       │
;             │                        │
;       fffaH ├────────────┤
;             │      NMI Vector        │
;       fffcH ├────────────┤
;             │     Reset Vector       │
;       fffeH ├────────────┤
;             │      IRQ Vector        │
;       ffffH └────────────┘
;
.PAGE
;
;   1.4 Program interrupt vector
;
;       ┌───────┬──────────────────────┐
;       │Vector address│                    Source                  │
;       ├───────┼──────────────────────┤
;       │  1FFAH       │                      NMI                   │
;       │  1FFBH       │      RTC wake up CPU every half second     │
;       ├───────┼──────────────────────┤
;       │  1FFCH       │                     RESET                  │
;       │  1FFDH       │       Reset Interrupt Service Routine      │
;       ├───────┼──────────────────────┤
;       │  1FFEH       │                      IRQ                   │
;       │  1FFFH       │  Timer base/Ext. Interrupt Service Routine │
;       └───────┴──────────────────────┘
;

;┌───────────────────────────────┐
;│                       I/O Port define                        │
;└───────────────────────────────┘

;STATUS
p_bank                    EQU     00h     ;R/W
p_int_ctrl                EQU     01H     ;R/W
p_int_clear               EQU     02H     ;W
p_bex_config              EQU     03H     ;W
P_04H_CPU_CLK_Ctrl        EQU     04H     ;W
P_PortA_Strobe_Pullhigh   EQU     05H     ;R/W
p_portA_config            EQU     06H     ;W
p_portA_dir_ctrl          EQU     07H     ;W

p_portA                   EQU     08H     ;R/W
p_portD                   EQU     09H     ;R/W
p_portB                   EQU     0AH     ;R/W
p_portC                   EQU     0BH     ;R/W
p_timer_base              EQU     0CH     ;W
P_0CH_TimeBaseSelect      EQU     0CH     ;W
p_bex_vol_id              EQU     0DH     ;W
P_0DH_BEXVolumeID         EQU     0DH     ;W
p_c32k_ctrl               EQU     0EH     ;W
P_0EH_Xcal32KCtrl         EQU     0EH     ;W


;;p_time_counter_ctrl       EQU     0FH     ;W
;;p_timer0_l                EQU     10H     ;R/W
;;p_timer0_h                EQU     11H     ;R/W
;;p_timer0_ctrl             EQU     12H     ;W
;;p_dac0                    EQU     13H     ;W

;;p_timer1_l                EQU     14H     ;R/W
;;p_timer1_h                EQU     15H     ;R/W
;;p_timer1_ctrl             EQU     16H     ;W
;;p_dac1                    EQU     17H     ;W

P_TimerCntControl         EQU     $0F     ;W
P_Timer0_Low              EQU     $10     ;R/W
P_Timer0_High             EQU     $11     ;R/W
P_PWM_Ch0Control          EQU     $12     ;W
P_PWM_Ch0Data             EQU     $13     ;W
P_Timer1_Low              EQU     $14     ;R/W
P_Timer1_High             EQU     $15     ;R/W
P_PWM_Ch1Control          EQU     $16     ;W
P_PWM_Ch1Data             EQU     $17     ;W


p_WakeUp_Ctrl              EQU     18H     ;W
P_18H_WakeUpCtrl:          EQU     18H     ;W


;UART
p_uart_ctrl1              EQU     19H     ;W
p_uart_ctrl2              EQU     1AH     ;W(ctrl)  R(stats)
p_uart_buffer             EQU     1BH     ;R/W
p_uart_baud_l             EQU     1EH     ;W
p_uart_baud_h             EQU     1FH     ;W

;
p_bmi_port0               EQU     20H     ;R/W
p_bmi_port1               EQU     21H     ;R/W
p_bmi_port2               EQU     22H     ;R/W
p_bmi_config              EQU     23H     ;W
p_lcd_opt                 EQU     24H     ;W
P_24H_LCD_option          EQU     24H     ;W
p_pump_ctrl               EQU     25H     ;W
P_25H_pump_control        EQU     25H     ;W
p_Vlcd_ctrl               EQU     26H     ;R/W
P_26H_VLCD_voltage_ctrl   EQU     26H     ;R/W
p_portCD_config           EQU     27H     ;W
p_portB_config            EQU     28H     ;W
p_portB_dir_ctrl          EQU     29H     ;W
p_portC_config            EQU     2AH     ;W
p_portC_dir_ctrl          EQU     2BH     ;W
p_portD_config            EQU     2CH     ;W
p_portD_dir_ctrl          EQU     2DH     ;W

;Serial
p_serial_data             EQU     30H     ;R/W
p_serial_addr1            EQU     31H     ;R/W
p_serial_addr2            EQU     32H     ;R/W
p_serial_addr3            EQU     33H     ;R/W
p_serial_ctrl             EQU     34H     ;R/W
p_serial_start            EQU     35H     ;R/W
p_serial_stop             EQU     36H     ;W

P_30H_Serial_SRAM_Data    EQU     30H     ;R/W
P_31H_Serial_SRAM_Addr1   EQU     31H     ;R/W
P_32H_Serial_SRAM_Addr2   EQU     32H     ;R/W
P_33H_Serial_SRAM_Addr3   EQU     33H     ;R/W
P_34H_Serial_SRAM_Ctrl    EQU     34H     ;R/W
P_35H_Serial_SRAM_Start   EQU     35H     ;R/W
P_36H_Serial_SRAM_Stop    EQU     36H     ;W

p_nmi_ctrl                EQU     38H     ;R/W
P_38H_NMI_Ctrl            EQU     38H     ;R/W
p_lvd_ctrl                EQU     39H     ;R/W
P_39H_LVD_Ctrl            EQU     39H     ;R/W
p_keyscan_ctrl            EQU     3AH     ;R/W
p_keyscan_port1           EQU     3BH     ;R/W
p_keyscan_port2           EQU     3CH     ;R/W
p_mirror_byte             EQU     3EH     ;R/W
p_swap_nibble             EQU     3FH     ;R/W

p_watchdog_clr            EQU     3031H   ;W


;谀哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪