📄 mk40x256vmd100.h
字号:
#define AIPS_PACRD_SP3_SHIFT 18
#define AIPS_PACRD_TP2_MASK 0x100000u
#define AIPS_PACRD_TP2_SHIFT 20
#define AIPS_PACRD_WP2_MASK 0x200000u
#define AIPS_PACRD_WP2_SHIFT 21
#define AIPS_PACRD_SP2_MASK 0x400000u
#define AIPS_PACRD_SP2_SHIFT 22
#define AIPS_PACRD_TP1_MASK 0x1000000u
#define AIPS_PACRD_TP1_SHIFT 24
#define AIPS_PACRD_WP1_MASK 0x2000000u
#define AIPS_PACRD_WP1_SHIFT 25
#define AIPS_PACRD_SP1_MASK 0x4000000u
#define AIPS_PACRD_SP1_SHIFT 26
#define AIPS_PACRD_TP0_MASK 0x10000000u
#define AIPS_PACRD_TP0_SHIFT 28
#define AIPS_PACRD_WP0_MASK 0x20000000u
#define AIPS_PACRD_WP0_SHIFT 29
#define AIPS_PACRD_SP0_MASK 0x40000000u
#define AIPS_PACRD_SP0_SHIFT 30
/* PACRE Bit Fields */
#define AIPS_PACRE_TP7_MASK 0x1u
#define AIPS_PACRE_TP7_SHIFT 0
#define AIPS_PACRE_WP7_MASK 0x2u
#define AIPS_PACRE_WP7_SHIFT 1
#define AIPS_PACRE_SP7_MASK 0x4u
#define AIPS_PACRE_SP7_SHIFT 2
#define AIPS_PACRE_TP6_MASK 0x10u
#define AIPS_PACRE_TP6_SHIFT 4
#define AIPS_PACRE_WP6_MASK 0x20u
#define AIPS_PACRE_WP6_SHIFT 5
#define AIPS_PACRE_SP6_MASK 0x40u
#define AIPS_PACRE_SP6_SHIFT 6
#define AIPS_PACRE_TP5_MASK 0x100u
#define AIPS_PACRE_TP5_SHIFT 8
#define AIPS_PACRE_WP5_MASK 0x200u
#define AIPS_PACRE_WP5_SHIFT 9
#define AIPS_PACRE_SP5_MASK 0x400u
#define AIPS_PACRE_SP5_SHIFT 10
#define AIPS_PACRE_TP4_MASK 0x1000u
#define AIPS_PACRE_TP4_SHIFT 12
#define AIPS_PACRE_WP4_MASK 0x2000u
#define AIPS_PACRE_WP4_SHIFT 13
#define AIPS_PACRE_SP4_MASK 0x4000u
#define AIPS_PACRE_SP4_SHIFT 14
#define AIPS_PACRE_TP3_MASK 0x10000u
#define AIPS_PACRE_TP3_SHIFT 16
#define AIPS_PACRE_WP3_MASK 0x20000u
#define AIPS_PACRE_WP3_SHIFT 17
#define AIPS_PACRE_SP3_MASK 0x40000u
#define AIPS_PACRE_SP3_SHIFT 18
#define AIPS_PACRE_TP2_MASK 0x100000u
#define AIPS_PACRE_TP2_SHIFT 20
#define AIPS_PACRE_WP2_MASK 0x200000u
#define AIPS_PACRE_WP2_SHIFT 21
#define AIPS_PACRE_SP2_MASK 0x400000u
#define AIPS_PACRE_SP2_SHIFT 22
#define AIPS_PACRE_TP1_MASK 0x1000000u
#define AIPS_PACRE_TP1_SHIFT 24
#define AIPS_PACRE_WP1_MASK 0x2000000u
#define AIPS_PACRE_WP1_SHIFT 25
#define AIPS_PACRE_SP1_MASK 0x4000000u
#define AIPS_PACRE_SP1_SHIFT 26
#define AIPS_PACRE_TP0_MASK 0x10000000u
#define AIPS_PACRE_TP0_SHIFT 28
#define AIPS_PACRE_WP0_MASK 0x20000000u
#define AIPS_PACRE_WP0_SHIFT 29
#define AIPS_PACRE_SP0_MASK 0x40000000u
#define AIPS_PACRE_SP0_SHIFT 30
/* PACRF Bit Fields */
#define AIPS_PACRF_TP7_MASK 0x1u
#define AIPS_PACRF_TP7_SHIFT 0
#define AIPS_PACRF_WP7_MASK 0x2u
#define AIPS_PACRF_WP7_SHIFT 1
#define AIPS_PACRF_SP7_MASK 0x4u
#define AIPS_PACRF_SP7_SHIFT 2
#define AIPS_PACRF_TP6_MASK 0x10u
#define AIPS_PACRF_TP6_SHIFT 4
#define AIPS_PACRF_WP6_MASK 0x20u
#define AIPS_PACRF_WP6_SHIFT 5
#define AIPS_PACRF_SP6_MASK 0x40u
#define AIPS_PACRF_SP6_SHIFT 6
#define AIPS_PACRF_TP5_MASK 0x100u
#define AIPS_PACRF_TP5_SHIFT 8
#define AIPS_PACRF_WP5_MASK 0x200u
#define AIPS_PACRF_WP5_SHIFT 9
#define AIPS_PACRF_SP5_MASK 0x400u
#define AIPS_PACRF_SP5_SHIFT 10
#define AIPS_PACRF_TP4_MASK 0x1000u
#define AIPS_PACRF_TP4_SHIFT 12
#define AIPS_PACRF_WP4_MASK 0x2000u
#define AIPS_PACRF_WP4_SHIFT 13
#define AIPS_PACRF_SP4_MASK 0x4000u
#define AIPS_PACRF_SP4_SHIFT 14
#define AIPS_PACRF_TP3_MASK 0x10000u
#define AIPS_PACRF_TP3_SHIFT 16
#define AIPS_PACRF_WP3_MASK 0x20000u
#define AIPS_PACRF_WP3_SHIFT 17
#define AIPS_PACRF_SP3_MASK 0x40000u
#define AIPS_PACRF_SP3_SHIFT 18
#define AIPS_PACRF_TP2_MASK 0x100000u
#define AIPS_PACRF_TP2_SHIFT 20
#define AIPS_PACRF_WP2_MASK 0x200000u
#define AIPS_PACRF_WP2_SHIFT 21
#define AIPS_PACRF_SP2_MASK 0x400000u
#define AIPS_PACRF_SP2_SHIFT 22
#define AIPS_PACRF_TP1_MASK 0x1000000u
#define AIPS_PACRF_TP1_SHIFT 24
#define AIPS_PACRF_WP1_MASK 0x2000000u
#define AIPS_PACRF_WP1_SHIFT 25
#define AIPS_PACRF_SP1_MASK 0x4000000u
#define AIPS_PACRF_SP1_SHIFT 26
#define AIPS_PACRF_TP0_MASK 0x10000000u
#define AIPS_PACRF_TP0_SHIFT 28
#define AIPS_PACRF_WP0_MASK 0x20000000u
#define AIPS_PACRF_WP0_SHIFT 29
#define AIPS_PACRF_SP0_MASK 0x40000000u
#define AIPS_PACRF_SP0_SHIFT 30
/* PACRG Bit Fields */
#define AIPS_PACRG_TP7_MASK 0x1u
#define AIPS_PACRG_TP7_SHIFT 0
#define AIPS_PACRG_WP7_MASK 0x2u
#define AIPS_PACRG_WP7_SHIFT 1
#define AIPS_PACRG_SP7_MASK 0x4u
#define AIPS_PACRG_SP7_SHIFT 2
#define AIPS_PACRG_TP6_MASK 0x10u
#define AIPS_PACRG_TP6_SHIFT 4
#define AIPS_PACRG_WP6_MASK 0x20u
#define AIPS_PACRG_WP6_SHIFT 5
#define AIPS_PACRG_SP6_MASK 0x40u
#define AIPS_PACRG_SP6_SHIFT 6
#define AIPS_PACRG_TP5_MASK 0x100u
#define AIPS_PACRG_TP5_SHIFT 8
#define AIPS_PACRG_WP5_MASK 0x200u
#define AIPS_PACRG_WP5_SHIFT 9
#define AIPS_PACRG_SP5_MASK 0x400u
#define AIPS_PACRG_SP5_SHIFT 10
#define AIPS_PACRG_TP4_MASK 0x1000u
#define AIPS_PACRG_TP4_SHIFT 12
#define AIPS_PACRG_WP4_MASK 0x2000u
#define AIPS_PACRG_WP4_SHIFT 13
#define AIPS_PACRG_SP4_MASK 0x4000u
#define AIPS_PACRG_SP4_SHIFT 14
#define AIPS_PACRG_TP3_MASK 0x10000u
#define AIPS_PACRG_TP3_SHIFT 16
#define AIPS_PACRG_WP3_MASK 0x20000u
#define AIPS_PACRG_WP3_SHIFT 17
#define AIPS_PACRG_SP3_MASK 0x40000u
#define AIPS_PACRG_SP3_SHIFT 18
#define AIPS_PACRG_TP2_MASK 0x100000u
#define AIPS_PACRG_TP2_SHIFT 20
#define AIPS_PACRG_WP2_MASK 0x200000u
#define AIPS_PACRG_WP2_SHIFT 21
#define AIPS_PACRG_SP2_MASK 0x400000u
#define AIPS_PACRG_SP2_SHIFT 22
#define AIPS_PACRG_TP1_MASK 0x1000000u
#define AIPS_PACRG_TP1_SHIFT 24
#define AIPS_PACRG_WP1_MASK 0x2000000u
#define AIPS_PACRG_WP1_SHIFT 25
#define AIPS_PACRG_SP1_MASK 0x4000000u
#define AIPS_PACRG_SP1_SHIFT 26
#define AIPS_PACRG_TP0_MASK 0x10000000u
#define AIPS_PACRG_TP0_SHIFT 28
#define AIPS_PACRG_WP0_MASK 0x20000000u
#define AIPS_PACRG_WP0_SHIFT 29
#define AIPS_PACRG_SP0_MASK 0x40000000u
#define AIPS_PACRG_SP0_SHIFT 30
/* PACRH Bit Fields */
#define AIPS_PACRH_TP7_MASK 0x1u
#define AIPS_PACRH_TP7_SHIFT 0
#define AIPS_PACRH_WP7_MASK 0x2u
#define AIPS_PACRH_WP7_SHIFT 1
#define AIPS_PACRH_SP7_MASK 0x4u
#define AIPS_PACRH_SP7_SHIFT 2
#define AIPS_PACRH_TP6_MASK 0x10u
#define AIPS_PACRH_TP6_SHIFT 4
#define AIPS_PACRH_WP6_MASK 0x20u
#define AIPS_PACRH_WP6_SHIFT 5
#define AIPS_PACRH_SP6_MASK 0x40u
#define AIPS_PACRH_SP6_SHIFT 6
#define AIPS_PACRH_TP5_MASK 0x100u
#define AIPS_PACRH_TP5_SHIFT 8
#define AIPS_PACRH_WP5_MASK 0x200u
#define AIPS_PACRH_WP5_SHIFT 9
#define AIPS_PACRH_SP5_MASK 0x400u
#define AIPS_PACRH_SP5_SHIFT 10
#define AIPS_PACRH_TP4_MASK 0x1000u
#define AIPS_PACRH_TP4_SHIFT 12
#define AIPS_PACRH_WP4_MASK 0x2000u
#define AIPS_PACRH_WP4_SHIFT 13
#define AIPS_PACRH_SP4_MASK 0x4000u
#define AIPS_PACRH_SP4_SHIFT 14
#define AIPS_PACRH_TP3_MASK 0x10000u
#define AIPS_PACRH_TP3_SHIFT 16
#define AIPS_PACRH_WP3_MASK 0x20000u
#define AIPS_PACRH_WP3_SHIFT 17
#define AIPS_PACRH_SP3_MASK 0x40000u
#define AIPS_PACRH_SP3_SHIFT 18
#define AIPS_PACRH_TP2_MASK 0x100000u
#define AIPS_PACRH_TP2_SHIFT 20
#define AIPS_PACRH_WP2_MASK 0x200000u
#define AIPS_PACRH_WP2_SHIFT 21
#define AIPS_PACRH_SP2_MASK 0x400000u
#define AIPS_PACRH_SP2_SHIFT 22
#define AIPS_PACRH_TP1_MASK 0x1000000u
#define AIPS_PACRH_TP1_SHIFT 24
#define AIPS_PACRH_WP1_MASK 0x2000000u
#define AIPS_PACRH_WP1_SHIFT 25
#define AIPS_PACRH_SP1_MASK 0x4000000u
#define AIPS_PACRH_SP1_SHIFT 26
#define AIPS_PACRH_TP0_MASK 0x10000000u
#define AIPS_PACRH_TP0_SHIFT 28
#define AIPS_PACRH_WP0_MASK 0x20000000u
#define AIPS_PACRH_WP0_SHIFT 29
#define AIPS_PACRH_SP0_MASK 0x40000000u
#define AIPS_PACRH_SP0_SHIFT 30
/* PACRI Bit Fields */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -