kinetis_flexcan.h

freescale k40/k60 can 例程

/*
 * File:    kinetis_flexcan.h
 * Purpose: Register and bit definitions
 */

#ifndef	__KINETIS_FLEXCAN_H
#define	__KINETIS_FLEXCAN_H

/* Common bit definition */
#define BIT0             (1L)
#define BIT1             (BIT0<<1)
#define BIT2             (BIT0<<2)
#define BIT3             (BIT0<<3)
#define BIT4             (BIT0<<4)
#define BIT5             (BIT0<<5)
#define BIT6             (BIT0<<6)
#define BIT7             (BIT0<<7)
#define BIT8             (BIT0<<8)
#define BIT9             (BIT0<<9)
#define BIT10            (BIT0<<10)
#define BIT11            (BIT0<<11)
#define BIT12            (0x00001000L)
#define BIT13            (0x00002000L)
#define BIT14            (0x00004000L)
#define BIT15            (0x00008000L)
#define BIT16            (0x00010000L)
#define BIT17            (0x00020000L)
#define BIT18            (0x00040000L)
#define BIT19            (0x00080000L)
#define BIT20            (0x00100000L)
#define BIT21            (0x00200000L)
#define BIT22            (0x00400000L)
#define BIT23            (0x00800000L)
#define BIT24            (0x01000000L)
#define BIT25            (0x02000000L)
#define BIT26            (0x04000000L)
#define BIT27            (0x08000000L)
#define BIT28            (0x10000000L)
#define BIT29            (0x20000000L)
#define BIT30            (0x40000000L)
#define BIT31            (0x80000000L)


/* FlexCAN module I/O Base Addresss */
#define FLEXCAN0_BASE			(0x40024000L)
#define FLEXCAN1_BASE			(0x400A4000L)

typedef volatile uint32 vuint32_t;

/*********************************************************************
*
* FlexCAN0 (FLEXCAN0)
*
*********************************************************************/

/* Register read/write macros */
#define FLEXCAN0_MCR                   (*(vuint32_t*)(FLEXCAN0_BASE))
#define FLEXCAN0_CTRL1                  (*(vuint32_t*)(FLEXCAN0_BASE+4))
#define FLEXCAN0_TIMER                 (*(vuint32_t*)(FLEXCAN0_BASE+8))
#define FLEXCAN0_TCR                   (*(vuint32_t*)(FLEXCAN0_BASE+0x0C))
#define FLEXCAN0_RXMGMASK               (*(vuint32_t*)(FLEXCAN0_BASE+0x10))
#define FLEXCAN0_RX14MASK              (*(vuint32_t*)(FLEXCAN0_BASE+0x14))
#define FLEXCAN0_RX15MASK              (*(vuint32_t*)(FLEXCAN0_BASE+0x18))
#define FLEXCAN0_ECR                   (*(vuint32_t*)(FLEXCAN0_BASE+0x1C))
#define FLEXCAN0_ESR1                  (*(vuint32_t*)(FLEXCAN0_BASE+0x20))
#define FLEXCAN0_IMASK2                (*(vuint32_t*)(FLEXCAN0_BASE+0x24))
#define FLEXCAN0_IMASK1                (*(vuint32_t*)(FLEXCAN0_BASE+0x28))
#define FLEXCAN0_IFLAG2                (*(vuint32_t*)(FLEXCAN0_BASE+0x2C))
#define FLEXCAN0_IFLAG1                (*(vuint32_t*)(FLEXCAN0_BASE+0x30))
#define FLEXCAN0_CTRL2                 (*(vuint32_t*)(FLEXCAN0_BASE+0x34))
#define FLEXCAN0_ESR2                  (*(vuint32_t*)(FLEXCAN0_BASE+0x38))
#define FLEXCAN0_FUREQ                 (*(vuint32_t*)(FLEXCAN0_BASE+0x3C))
#define FLEXCAN0_FUACK                 (*(vuint32_t*)(FLEXCAN0_BASE+0x40))
#define FLEXCAN0_CRCR                  (*(vuint32_t*)(FLEXCAN0_BASE+0x44))
#define FLEXCAN0_RXFGMASK              (*(vuint32_t*)(FLEXCAN0_BASE+0x48))
#define FLEXCAN0_RXFIR                 (*(vuint32_t*)(FLEXCAN0_BASE+0x4C))
#define FLEXCAN0_DBG1                  (*(vuint32_t*)(FLEXCAN0_BASE+0x58))
#define FLEXCAN0_DBG2                  (*(vuint32_t*)(FLEXCAN0_BASE+0x5C))

#define FLEXCAN0_IMEUR                 FLEXCAN0_FUREQ
#define FLEXCAN0_LRFR                  FLEXCAN0_FUACK					


/* Message Buffers */
#define FLEXCAN0_MB0_CS                (*(vuint32_t*)(FLEXCAN0_BASE+0x80))
#define FLEXCAN0_MB0_ID                (*(vuint32_t*)(FLEXCAN0_BASE+0x84))
#define FLEXCAN0_MB0_WORD0             (*(vuint32_t*)(FLEXCAN0_BASE+0x88))
#define FLEXCAN0_MB0_WORD1             (*(vuint32_t*)(FLEXCAN0_BASE+0x8C))

#define FLEXCAN0_MBn_CS(n)			(*(vuint32_t*)(FLEXCAN0_BASE+0x80+n*0x10))	
#define FLEXCAN0_MBn_ID(n)			(*(vuint32_t*)(FLEXCAN0_BASE+0x84+n*0x10))
#define FLEXCAN0_MBn_WORD0(n)		(*(vuint32_t*)(FLEXCAN0_BASE+0x88+n*0x10))
#define FLEXCAN0_MBn_WORD1(n)		(*(vuint32_t*)(FLEXCAN0_BASE+0x8C+n*0x10))

/* Rx Individual Mask Registers */
#define FLEXCAN0_RXIMR0                (*(vuint32_t*)(FLEXCAN0_BASE+0x880))
#define FLEXCAN0_RXIMRn(n)             (*(vuint32_t*)(FLEXCAN0_BASE+0x880+n*4))

/* Rx FIFO ID Filter Table Element 0 to 127 */
#define FLEXCAN0_IDFLT_TAB0		(*(vuint32_t*)(FLEXCAN0_BASE+0xE0))
#define FLEXCAN0_IDFLT_TAB(n)		(*(vuint32_t*)(FLEXCAN0_BASE+0xE0+(n*4)))
//#define FLEXCAN0_IDFLT_TAB(n)		(*(vuint32_t*)(FLEXCAN0_BASE+0xE0+(n<<2)))

/* Memory Error Control Register */
#define FLEXCAN0_MECR					*(vuint32_t*)(FLEXCAN0_BASE+0x3B70))

/* Error Injection Address Register */
#define FLEXCAN0_ERRIAR					*(vuint32_t*)(FLEXCAN0_BASE+0x3B74))

/* Error Injection Data Pattern Register */
#define FLEXCAN0_ERRIDPR				*(vuint32_t*)(FLEXCAN0_BASE+0x3B78))

/* Error Injection Parity Pattern Register */
#define FLEXCAN0_ERRIPPR				*(vuint32_t*)(FLEXCAN0_BASE+0x3B7C))

/* Error Report Address Register */
#define FLEXCAN0_RERRAR					*(vuint32_t*)(FLEXCAN0_BASE+0x3B80))

/* Error Report Data Register */
#define FLEXCAN0_RERRDR					*(vuint32_t*)(FLEXCAN0_BASE+0x3B84))

/* Error Report Syndrome Register */
#define FLEXCAN0_RERRSYNR				*(vuint32_t*)(FLEXCAN0_BASE+0x3B88))

/* Error Status Register */
#define FLEXCAN0_ERRSR					*(vuint32_t*)(FLEXCAN0_BASE+0x3B8C))


/*********************************************************************
*
* FlexCAN1 (FLEXCAN1)
*
*********************************************************************/
/* Register read/write macros */
#define FLEXCAN1_MCR                   (*(vuint32_t*)(FLEXCAN1_BASE))
#define FLEXCAN1_CTRL1                 (*(vuint32_t*)(FLEXCAN1_BASE+4))
#define FLEXCAN1_TIMER                 (*(vuint32_t*)(FLEXCAN1_BASE+8))
#define FLEXCAN1_TCR                   (*(vuint32_t*)(FLEXCAN1_BASE+0x0C))
#define FLEXCAN1_RXMGMASK              (*(vuint32_t*)(FLEXCAN1_BASE+0x10))
#define FLEXCAN1_RX14MASK              (*(vuint32_t*)(FLEXCAN1_BASE+0x14))
#define FLEXCAN1_RX15MASK              (*(vuint32_t*)(FLEXCAN1_BASE+0x18))
#define FLEXCAN1_ECR                   (*(vuint32_t*)(FLEXCAN1_BASE+0x1C))
#define FLEXCAN1_ESR1                  (*(vuint32_t*)(FLEXCAN1_BASE+0x20))
#define FLEXCAN1_IMASK2                (*(vuint32_t*)(FLEXCAN1_BASE+0x24))
#define FLEXCAN1_IMASK1                (*(vuint32_t*)(FLEXCAN1_BASE+0x28))
#define FLEXCAN1_IFLAG2                (*(vuint32_t*)(FLEXCAN1_BASE+0x2C))
#define FLEXCAN1_IFLAG1                (*(vuint32_t*)(FLEXCAN1_BASE+0x30))
#define FLEXCAN1_CTRL2                 (*(vuint32_t*)(FLEXCAN1_BASE+0x34))
#define FLEXCAN1_ESR2                  (*(vuint32_t*)(FLEXCAN1_BASE+0x38))
#define FLEXCAN1_FUREQ                 (*(vuint32_t*)(FLEXCAN1_BASE+0x3C))
#define FLEXCAN1_FUACK                 (*(vuint32_t*)(FLEXCAN1_BASE+0x40))
#define FLEXCAN1_CRCR                  (*(vuint32_t*)(FLEXCAN1_BASE+0x44))
#define FLEXCAN1_RXFGMASK              (*(vuint32_t*)(FLEXCAN1_BASE+0x48))
#define FLEXCAN1_RXFIR                 (*(vuint32_t*)(FLEXCAN1_BASE+0x4C))
#define FLEXCAN1_DBG1                  (*(vuint32_t*)(FLEXCAN1_BASE+0x58))
#define FLEXCAN1_DBG2                  (*(vuint32_t*)(FLEXCAN1_BASE+0x5C))

#define FLEXCAN1_IMEUR                 FLEXCAN1_FUREQ
#define FLEXCAN1_LRFR                  FLEXCAN1_FUACK					

/* Message Buffers */
#define FLEXCAN1_MB0_CS                (*(vuint32_t*)(FLEXCAN1_BASE+0x80))
#define FLEXCAN1_MB0_ID                (*(vuint32_t*)(FLEXCAN1_BASE+0x84))
#define FLEXCAN1_MB0_WORD0             (*(vuint32_t*)(FLEXCAN1_BASE+0x88))
#define FLEXCAN1_MB0_WORD1             (*(vuint32_t*)(FLEXCAN1_BASE+0x8C))

#define FLEXCAN1_MBn_CS(n)		        (*(vuint32_t*)(FLEXCAN1_BASE+0x80+n*0x10))	
#define FLEXCAN1_MBn_ID(n)				(*(vuint32_t*)(FLEXCAN1_BASE+0x84+n*0x10))
#define FLEXCAN1_MBn_WORD0(n)			(*(vuint32_t*)(FLEXCAN1_BASE+0x88+n*0x10))
#define FLEXCAN1_MBn_WORD1(n)			(*(vuint32_t*)(FLEXCAN1_BASE+0x8C+n*0x10))

/* Rx Individual Mask Registers */
#define FLEXCAN1_RXIMR0                (*(vuint32_t*)(FLEXCAN1_BASE+0x880))
#define FLEXCAN1_RXIMRn(n)             (*(vuint32_t*)(FLEXCAN1_BASE+0x880+n*4))


/* Rx FIFO ID Filter Table Element 0 to 127 */
#define FLEXCAN1_IDFLT_TAB0		(*(vuint32_t*)(FLEXCAN1_BASE+0xE0))
#define FLEXCAN1_IDFLT_TAB(n)		(*(vuint32_t*)(FLEXCAN1_BASE+0xE0+(n<<2)))

/* Memory Error Control Register */
#define FLEXCAN1_MECR					*(vuint32_t*)(FLEXCAN1_BASE+0x7B70))	

/* Error Injection Address Register */
#define FLEXCAN1_ERRIAR					*(vuint32_t*)(FLEXCAN1_BASE+0x3B74))

/* Error Injection Data Pattern Register */
#define FLEXCAN1_ERRIDPR				*(vuint32_t*)(FLEXCAN1_BASE+0x3B78))

/* Error Injection Parity Pattern Register */
#define FLEXCAN1_ERRIPPR				*(vuint32_t*)(FLEXCAN1_BASE+0x3B7C))

/* Error Report Address Register */
#define FLEXCAN1_RERRAR					*(vuint32_t*)(FLEXCAN1_BASE+0x3B80))

/* Error Report Data Register */
#define FLEXCAN1_RERRDR					*(vuint32_t*)(FLEXCAN1_BASE+0x3B84))

/* Error Report Syndrome Register */
#define FLEXCAN1_RERRSYNR				*(vuint32_t*)(FLEXCAN1_BASE+0x3B88))

/* Error Status Register */
#define FLEXCAN1_ERRSR					*(vuint32_t*)(FLEXCAN1_BASE+0x3B8C))

/* Bit definitions and macros for FLEXCAN_MCR */
#define FLEXCAN_MCR_MAXMB(x)           (((x)&0x0000007F)<<0)
#define FLEXCAN_MCR_IDAM(x)            (((x)&0x00000003)<<8)
#define FLEXCAN_MCR_MAXMB_MASK			(0x0000007F)
#define FLEXCAN_MCR_IDAM_MASK			(0x00000300)
#define FLEXCAN_MCR_IDAM_BIT_NO        (8)
#define FLEXCAN_MCR_AEN                (0x00001000)
#define FLEXCAN_MCR_LPRIO_EN           (0x00002000)
#define FLEXCAN_MCR_IRMQ               (0x00010000)
#define FLEXCAN_MCR_SRX_DIS            (0x00020000)
#define FLEXCAN_MCR_DOZE               (0x00040000)
#define FLEXCAN_MCR_WAK_SRC            (0x00080000)
#define FLEXCAN_MCR_LPM_ACK            (0x00100000)
#define FLEXCAN_MCR_WRN_EN             (0x00200000)
#define FLEXCAN_MCR_SLF_WAK            (0x00400000)
#define FLEXCAN_MCR_SUPV               (0x00800000)
#define FLEXCAN_MCR_FRZ_ACK            (0x01000000)
#define FLEXCAN_MCR_SOFT_RST           (0x02000000)
#define FLEXCAN_MCR_WAK_MSK            (0x04000000)
#define FLEXCAN_MCR_NOT_RDY            (0x08000000)
#define FLEXCAN_MCR_HALT               (0x10000000)
#define FLEXCAN_MCR_FEN                (0x20000000)
#define FLEXCAN_MCR_FRZ                (0x40000000)
#define FLEXCAN_MCR_MDIS               (0x80000000)

/* Bit definitions and macros for FLEXCAN_CTRL */
#define FLEXCAN_CTRL_PROPSEG(x)        (((x)&0x00000007L)<<0)
#define FLEXCAN_CTRL_LOM               (0x00000008)
#define FLEXCAN_CTRL_LBUF              (0x00000010)
#define FLEXCAN_CTRL_TSYNC             (0x00000020)
#define FLEXCAN_CTRL_BOFF_REC          (0x00000040)
#define FLEXCAN_CTRL_SMP               (0x00000080)
#define FLEXCAN_CTRL_RWRN_MSK          (0x00000400)
#define FLEXCAN_CTRL_TWRN_MSK          (0x00000800)
#define FLEXCAN_CTRL_LPB               (0x00001000L)
#define FLEXCAN_CTRL_CLK_SRC           (0x00002000)
#define FLEXCAN_CTRL_ERR_MSK           (0x00004000)
#define FLEXCAN_CTRL_BOFF_MSK          (0x00008000)
#define FLEXCAN_CTRL_PSEG2(x)          (((x)&0x00000007L)<<16)
#define FLEXCAN_CTRL_PSEG1(x)          (((x)&0x00000007L)<<19)
#define FLEXCAN_CTRL_RJW(x)            (((x)&0x00000003L)<<22)
#define FLEXCAN_CTRL_PRESDIV(x)        (((x)&0x000000FFL)<<24)

/* Bit definitions and macros for FLEXCAN_CTRL2 */
#define FLEXCAN_CTRL2_IMEUEN	        (BIT31)
#define FLEXCAN_CTRL2_RFFN             (0x0F000000L)
#define FLEXCAN_CTRL2_RFFN_BIT_NO      (24)
#define FLEXCAN_CTRL2_TASD             (0x00F80000L)
#define FLEXCAN_CTRL2_TASD_BIT_NO      (19)
#define FLEXCAN_CTRL2_MRP              (BIT18)
#define FLEXCAN_CTRL2_RRS              (BIT17)
#define FLEXCAN_CTRL2_EACEN            (BIT16)
#define FLEXCAN_CTRL2_MUMASK           (BIT1)
#define FLEXCAN_CTRL2_FUMASK           (BIT0)
#define FLEXCAN_CTRL2_LOSTRLMSK		   (BIT2)
#define FLEXCAN_CTRL2_LOSTRMMSK		   (BIT1)
#define FLEXCAN_CTRL2_IMEUMASK		   (BIT0)
#define FLEXCAN_set_rffn(ctrl2,rffn)	ctrl2 = ((ctrl2) & ~FLEXCAN_CTRL2_RFFN) | ((rffn & 0xF)<<FLEXCAN_CTRL2_RFFN_BIT_NO)


/* Bit definitions and macros for FLEXCAN_TIMER */
#define FLEXCAN_TIMER_TIMER(x)         (((x)&0x0000FFFF)<<0)

/* Bit definitions and macros for FLEXCAN_TCR */
#define FLEXCAN_TCR_DSCACK             (0x00000100)
#define FLEXCAN_TCR_BIT_CLS            (0x00000200)
#define FLEXCAN_TCR_TRD                (0x00000400)

/* Bit definitions and macros for FLEXCAN_RXGMASK */
#define FLEXCAN_RXGMASK_MI0            (0x00000001)
#define FLEXCAN_RXGMASK_MI1            (0x00000002)
#define FLEXCAN_RXGMASK_MI2            (0x00000004)
#define FLEXCAN_RXGMASK_MI3            (0x00000008)
#define FLEXCAN_RXGMASK_MI4            (0x00000010)
#define FLEXCAN_RXGMASK_MI5            (0x00000020)
#define FLEXCAN_RXGMASK_MI6            (0x00000040)
#define FLEXCAN_RXGMASK_MI7            (0x00000080)
#define FLEXCAN_RXGMASK_MI8            (0x00000100)
#define FLEXCAN_RXGMASK_MI9            (0x00000200)
#define FLEXCAN_RXGMASK_MI10           (0x00000400)
#define FLEXCAN_RXGMASK_MI11           (0x00000800)
#define FLEXCAN_RXGMASK_MI12           (0x00001000)
#define FLEXCAN_RXGMASK_MI13           (0x00002000)
#define FLEXCAN_RXGMASK_MI14           (0x00004000)