armia_iacxl10_2004_3_16.cpp

自己编写的ARM处理器的指令集仿真

     rdlo = rst;
     rdhi = rst >> 32;
     bit  = rdhi;
     if( tmp.mul_ext.S1 == 1 )
         {
            CPSR.N = bit[31];
            if( (rdhi == 0) && (rdlo == 0) )
                  CPSR.Z = 1;
            else
                  CPSR.Z = 0;
         }
     if( (tmp.mul_ext.Rdlo == 15) || (tmp.mul_ext.Rdhi == 15) )
           pc_changed = true;
}

void ARMISS_stru::UMLAL()
{
     ARM_type0_stru&  tmp  = ARM_type0;
     UNL&                 rdlo = getreg( tmp.mul_ext.Rdlo );
     UNL&                 rdhi = getreg( tmp.mul_ext.Rdhi );
     UNL                  rs   = getregd( tmp.mul_ext.Rs );
     UNL                  rm   = getregd( tmp.mul_ext.Rm );
     bit32_stru           bit;
     long long            rst  = 1;
     int                  C;
     
     if( tmp.mul_ext.Rs == 15 ) rs   = rs   + 8;
     if( tmp.mul_ext.Rm == 15 ) rm   = rm   + 8;
     if( tmp.mul_ext.Rdlo == 15 ) rdlo = rdlo + 8;
     if( tmp.mul_ext.Rdhi == 15 ) rdhi = rdhi + 8;      
     rst = rst * (unsigned)(rm) * (unsigned)(rs) + (unsigned)(rdlo);
     if( rst > (unsigned)(0xffffffff) )
           C = 1;
     else
           C = 0;
     rdlo =(unsigned)(rst);
     rst  = rst >> 32;
     rdhi = (unsigned)(rdhi) + (unsigned)(rst) + C;
     bit  = rdhi;
     if( tmp.mul_ext.S1 == 1 )
       {
          CPSR.N = bit[31];
          if( (rdlo == 0) && (rdhi == 0) )
               CPSR.Z = 0;
          else
               CPSR.Z = 1;
       }
}
               
void ARMISS_stru::UMULL()
{   
     ARM_type0_stru&  tmp  = ARM_type0;
     UNL                  rdlo = getregd( tmp.mul_ext.Rdlo );
     UNL                  rdhi = getregd( tmp.mul_ext.Rdhi );
     UNL                  rs   = getregd( tmp.mul_ext.Rs );
     UNL                  rm   = getregd( tmp.mul_ext.Rm );
     UNL&                 rthi = getreg( tmp.mul_ext.Rdhi );
     UNL&                 rtlo = getreg( tmp.mul_ext.Rdlo );
     bit32_stru           bit;
     long long            rst  = 1;

   

   if( executable() )
    {
     if( tmp.mul_ext.Rs == 15 ) rs   = rs   + 8;
     if( tmp.mul_ext.Rm == 15 ) rm   = rm   + 8;
     if( tmp.mul_ext.Rdlo == 15 ) rdlo = rdlo + 8;
     if( tmp.mul_ext.Rdhi == 15 ) rdhi = rdhi + 8;
     rst  = rst * (unsigned)(rm) * (unsigned)(rs);
     
     rdlo = (unsigned)(rst);
     rdhi = rst >> 32;
     bit  = rdhi;
     rthi = rdhi;
     rtlo = rdlo;
     if( tmp.mul_ext.S1 == 1 )
         {
            CPSR.N = bit[31];
            if( (rdhi == 0) && (rdlo == 0) )
                  CPSR.Z = 1;
            else
                  CPSR.Z = 0;
         }  
        if( (tmp.mul_ext.Rdlo == 15) || (tmp.mul_ext.Rdhi == 15) )
                  pc_changed = true;
       
    }  
}
 
void ARMISS_stru::SWPB()
{
      ARM_type0_stru&  tmp = ARM_type0;
      UNL&             rd  = getreg( tmp.mul_ext.Rd2 );
      UNL              rm  = getregd( tmp.mul_ext.Rm );
      UNL              rn  = getregd( tmp.mul_ext.Rn2 );
      UNL              addr;
    
   if( executable() )
   {
     if( tmp.mul_ext.Rn2 == 15 ) rn   = rn   + 8;
     if( tmp.mul_ext.Rm == 15 ) rm   = rm   + 8;
     addr = rn;
     nrw  = false;
     (*pmemfun)(addr,&data,nrw,0,&abort);
     if( abort ) data_abt = true;
     if( !data_abt ) rd   = data & 0xff;
     data = rm & 0xff;
     nrw  = true;
     (*pmemfun)(addr,&data,nrw,0,&abort);
   }
}

void ARMISS_stru::SWP()
{
     ARM_type0_stru&  tmp = ARM_type0;
     UNL&             rd  = getreg( tmp.mul_ext.Rd2 );
     UNL              rm  = getregd( tmp.mul_ext.Rm );
     UNL              rn  = getregd( tmp.mul_ext.Rn2 );
     int              op;
     bit32_stru       bit;

   if( executable() )
   {
     if( tmp.mul_ext.Rn2 == 15 ) rn   = rn   + 8;
     if( tmp.mul_ext.Rm == 15 )  rm   = rm   + 8;
     op = rn & 0x3;
     (*pmemfun)(rn,&data,false,2,&abort);
     if( abort ) data_abt = true;
     bit = data;
     switch( op )
     {
       case  0: bit.rotate(0);
                break;
       case  1: bit.rotate(8);
                break;
       case  2: bit.rotate(16);
                break;
       case  3: bit.rotate(24);
                break;
       default: break;
     }
    if( !data_abt ) rd   = bit;
    data = rm;
    (*pmemfun)(rn,&data,true,2,&abort);
    if( tmp.mul_ext.Rd2 == PC ) pc_changed = true;
   }
} 

void ARMISS_stru::LDRH()
{
   ARM_type0_stru&      tmp = ARM_type0;
   bit32_stru           bit;
   UNL&                 rd  = getreg( tmp.mul_ext.Rd2 );
   UNL                  addr;
  if( executable() )
  {
   addr = Addressing_mod3();
   bit  = addr;
   if( bit[0] == 0 )
     {
         (*pmemfun)(addr,&data,false,1,&abort);
          if( abort ) data_abt = true;
     }
   
   if( tmp.mul_ext.Rd2 == 15 )
      pc_changed = true;
   if( !data_abt )  rd = data; 
  }
  
}

void ARMISS_stru::LDRSB()
{
   ARM_type0_stru&      tmp = ARM_type0;
   bit32_stru           bit;
   UNL&                 rd  = getreg( tmp.mul_ext.Rd2 );
   UNL                  addr;
  
  if( executable() )
 {
   addr = Addressing_mod3();
   (*pmemfun)(addr,&data,false,0,&abort);
   if( abort ) data_abt = true; 
   bit = data;
   if( bit[7] == 1 )
      {
         data = data & 0xff;
         data = data | 0xffffff00;
      }
   else
         data = data & 0xff;
         
   if( !data_abt ) rd  = data;
  }
}

void ARMISS_stru::LDRSH()
{
   ARM_type0_stru&      tmp = ARM_type0;
   bit32_stru           bit;
   UNL&                 rd  = getreg( tmp.mul_ext.Rd2 );
   UNL                  addr;
  
  if( executable() )
 {
   addr = Addressing_mod3();
 
   bit  = addr;
   if( bit[0] == 0 )
      {
          (*pmemfun)(addr,&data,false,1,&abort);
          if( abort ) data_abt = true;
          bit = data;
          data = data & 0xffff;
          if( bit[15] == 1 )
               data = data | 0xffff0000;
                       
      }
  if( !data_abt )
  {  rd = data;
     pc_changed = (tmp.mul_ext.Rd2==PC)? true:false;
  }
 }
  
}
     
void ARMISS_stru::STRH()
{
   ARM_type0_stru&      tmp = ARM_type0;
   bit32_stru           bit;
   UNL                  rd  = getregd( tmp.mul_ext.Rd2 );
   UNL                  addr;

   if( executable() )
  {
   addr = Addressing_mod3();
   bit  = addr;
   if( bit[0] == 0 )
   { 
       data = rd & 0xffff;
      
   }
   else
       data = rand();
       (*pmemfun)(addr,&data,true,1,&abort);
       if( abort ) data_abt = true;
  }
}

void ARMISS_stru::BL()
{
     ARM_type5_stru&   tmp = ARM_type5;
     bit32_stru        bit;
     UNL&              lr  = getreg( 14 );
     long              addr;

    
     if( executable() )
    {
      bit  = tmp.offset;
      addr = tmp.offset;
      if( bit[23] == 1 )
         addr = addr | 0xff000000;
      else
         addr = addr & 0x00ffffff;
      addr = addr << 2;
    
      if( tmp.L == 1 )
           lr = r_gen[PC] + 4;
      r_gen[PC]  = r_gen[PC] + 8 + addr;
      pc_changed = true;
    }
}
     
         


int ARMISS_stru::SWI()
{
      ARM_type7_stru&   tmp = ARM_type7;
      bit32_stru        bit;
      UNL               addr;

     
      switch( tmp.swinum )
     {
       case AngelSWI_ARM        :  addr = r_gen[1];
                                  
            switch( r_gen[0] )
	      {//llj
              case AngelSWI_Reason_Write :
                          SWIWrite( Read_Word( addr ),Read_Word( addr + 4 ), Read_Word( addr + 8 ) );
                          break;
              case AngelSWI_Reason_HeapInfo:
                         addr = Read_Word( addr );
                         Write_Word(addr,0);
                         Write_Word(addr+4,memptr.memsize);
                         Write_Word(addr+8,memptr.memsize);
                         Write_Word(addr+12,memptr.memsize);
                         break;
              case AngelSWI_Reason_Open:
                         SWIOpen( Read_Word( addr ), Read_Word( addr + 4 ) );
                         break;//open a file ,the file can be diskette
              case AngelSWI_Reason_Command:
                        WriteCommandLineTo( Read_Word( addr ) );
                        break;
			//llj
              case AngelSWI_Reason_ReportException:
                        if( r_gen[1] == ADP_Stopped_ApplicationExit )
                             r_gen[0] = 0;
                        else
                             r_gen[0] = -1;
                        
                        Emulate = false;
                        break;
              case ADP_Stopped_ApplicationExit:
                        r_gen[0] = 0;
                        Emulate = false;
                        break;//Stop ISS;
			//llj
              case AngelSWI_Reason_Read:
                        SWIRead(Read_Word( addr ), Read_Word( addr+4 ),Read_Word( addr+8 ));
                        
                        break;   
              case AngelSWI_Reason_WriteC:
                             (void)fputc ((int)Read_Byte(addr), stdout);
                          cout<<endl;
                          break;  
			  //llj  
              default   : break;
           }
                          break;
              default   : break;
     }
  
  return 0;          
} //system call ;

void ARMISS_stru::LDC()
{
    addr_stru   paddr;
    UNL         addr;

  if( executable() )
  {
    if( copro_pt )
       (*pcopro)(&ncpa,&ncpb,&data);
    if( ncpa ) undef_abt = true;
    else
      {
            while( ncpb ) (*pcopro)(&ncpa,&ncpb,&data);
            paddr = Addressing_mod5();
            addr  = paddr.start;
            while( ncpa ) 
            {
               (*pmemfun)(addr,&data,false,2,&abort);
               if( abort ) data_abt = true;
               addr = addr + 4;
            }
       assert( paddr.end == addr );
      }
   }            
  
}

void ARMISS_stru::STC()
{
 
    addr_stru   paddr;
    UNL         addr;

  if( executable() )
  {
    if( copro_pt )
       (*pcopro)(&ncpa,&ncpb,&data);
    if( ncpa ) undef_abt = true;
    else
      {
            while( ncpb ) (*pcopro)(&ncpa,&ncpb,&data);
            paddr = Addressing_mod5();
            addr  = paddr.start;
            while( ncpa ) 
            {
               (*pmemfun)(addr,&data,true,2,&abort);
               if( abort ) data_abt = true;
               addr = addr + 4;
            }
       assert( paddr.end == addr );
      }
   }            
  

}

void ARMISS_stru::CDP()
{

   if( copro_pt )
  {
     (*pcopro)(&ncpa,&ncpb,&data);
     if( ncpa ) undef_abt = true;
     else while(ncpb) (*pcopro)(&ncpa,&ncpb,&data);
     while( !ncpa ) (*pcopro)(&ncpa,&ncpb,&data);
  }

}

void ARMISS_stru::MCR()
{
  ARM_type7_stru&  tmp = ARM_type7;
  UNL&             Rd  = getreg( tmp.Rd );

  if( copro_pt ) (*pcopro)(&ncpa,&ncpb,&data);
  if( ncpa ) undef_abt = true;
  else while( ncpb ) (*pcopro)(&ncpa,&ncpb,&data);
  data = (tmp.Rd==PC) ? Rd+8 : Rd;
  (*pcopro)(&ncpa,&ncpb,&data);
 
}

void ARMISS_stru::MRC()
{
  ARM_type7_stru&  tmp = ARM_type7;
  UNL&             Rd  = getreg( tmp.Rd );

  if( copro_pt ) (*pcopro)(&ncpa,&ncpb,&data);
  if( ncpa ) undef_abt = true;
  else while( ncpb ) (*pcopro)(&ncpa,&ncpb,&data);
 
 (*pcopro)(&ncpa,&ncpb,&data);
  Rd = data;
  if( tmp.Rd == PC ) pc_changed = true;
  
}


void ARMISS_stru::run()
{
  static int sta=0;
         int inter,num=0;
  
	 printf("in run(),commandline=%s\n",commandline);
  if( sta==0 ) { sta++; init(); } 
    while( Emulate )
     {
     
       fetch();
       decode();
    
       if( Endcond == 143 ) { break; }
       if( irq_pt )
          (*pirq)(&nirq);
       if( fiq_pt )
         (*pfiq)(&nfiq);
       if( !nirq ) {irq_ext = true;}//该语句用于检测中断是否发生
	   //if(!nfiq) {fiq_ext = true;}//为了调试方便快中断检测被注释掉；
       inter = check_except();//中断异常的优先级处理并实现中断响应过程；
	                          //函数的实现在armcommon.cpp中；
       if( inter == 1 )//中断异常没有发生；
          if( !pc_changed ) //PC值未被指令修改；
			  r_gen[PC] = r_gen[PC]+4;
          else              
			  pc_changed = false;
       else pc_changed = false;
      
       
      }
         
     
}

void ARMISS_stru::step()
{
  // static int sta=0;
         int inter,num=0;
   
	 //if( sta==0 ) { sta++; init(); } 
 
       fetch();
       decode();
    
       // if( Endcond == 1 ) exit(0);//{ break; }
       if( irq_pt )
          (*pirq)(&nirq);
       if( fiq_pt )
         (*pfiq)(&nfiq);
       if( !nirq ) {irq_ext = true;}
       inter = check_except();
       if( inter == 1 )
          if( !pc_changed ) r_gen[PC] = r_gen[PC]+4;
          else              {pc_changed = false;}
       else pc_changed = false;
   
     
}

void ARMISS_stru::mem_reg(MEMFUN p,memarg_stru ptr)
{
     pmemfun = p;
     memptr  = ptr;
     // r_irq[0] = memptr.memsize;
    // r_fiq[5] = memptr.memsize;
    // r_abt[0] = memptr.memsize;
    // r_und[0] = memptr.memsize;
     
    
}//memory register;