📄 armia_iacxl10_2004_3_16.cpp
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}UNL ARMISS_stru::SUB(){ long rst,a,b; bit32_stru b1,b2,b3; int op; a = oper; b = shifter.operand; rst = a - b ; if( ( update_flags ) && ( des_reg == 15 ) ) { CPSR = SPSR[getid()];} else if ( update_flags ) { b1 = a; b2 = (-1)*b; b3 = rst; CPSR.N = b3[31]; CPSR.Z = ( rst == 0 )? 1 : 0; op = b1[31]; op = op << 1; op = op + b2[31]; op=op<<1;op=op+b3[31]; if( b == 0 ) { CPSR.C = 1; CPSR.V = 0; } else switch( op ) { case 0 : CPSR.C = 0; CPSR.V = 0; break; case 1 : CPSR.C = 0; CPSR.V = 1; break; case 2 : CPSR.C = 1; CPSR.V = 0; break; case 3 : CPSR.C = CPSR.V = 0; break; case 4 : CPSR.C = 1; CPSR.V = 0; break; case 5 : CPSR.C = CPSR.V = 0; break; case 6 : CPSR.C = CPSR.V = 1; break; case 7 : CPSR.C = 1; CPSR.V = 0; break; } } return ( rst );}UNL ARMISS_stru::RSB(){ long rst,a,b; bit32_stru b1,b2,b3; int op; b = oper; a = shifter.operand; rst = a - b ; if( ( update_flags ) && ( des_reg == 15 ) ) CPSR = SPSR[getid()]; else if ( update_flags ) { b1 = a; b2 = (-1)*b; b3 = rst; CPSR.N = b3[31]; CPSR.Z = ( rst == 0 )? 1 : 0; op = b1[31]; op = op << 1; op = op + b2[31]; op=op<<1;op=op+b3[31]; if( b == 0 ) { CPSR.C = 1; CPSR.V=0;} else switch( op ) { case 0 : CPSR.C = 0; CPSR.V = 0; break; case 1 : CPSR.C = 0; CPSR.V = 1; break; case 2 : CPSR.C = 1; CPSR.V = 0; break; case 3 : CPSR.C = CPSR.V = 0; break; case 4 : CPSR.C = 1; CPSR.V = 0; break; case 5 : CPSR.C = CPSR.V = 0; break; case 6 : CPSR.C = CPSR.V = 1; break; case 7 : CPSR.C = 1; CPSR.V = 0; break; } } return ( rst );}UNL ARMISS_stru::ADD(){ long rst,a,b,op; bit32_stru b1,b2,b3; a = oper; b = shifter.operand; rst = a + b ; if( ( update_flags ) && ( des_reg == 15 ) ) CPSR = SPSR[getid()]; else if( update_flags ) { b1 = a; b2 = b; b3 = rst; op = b1[31]; op = (op << 1) + b2[31]; op = (op << 1) + b3[31]; CPSR.N = b3[31]; CPSR.Z = rst == 0? 1:0; switch( op ) { case 1 : CPSR.C = CPSR.V = 1; break; case 2 : case 3 : case 4 : case 5 : CPSR.C = ( b1 + b2 ); CPSR.V = 0; break; case 6 : CPSR.C = CPSR.V = 1; break; case 7 : CPSR.C = ( b1 + b2 ); CPSR.V = 0; break; } } return rst;} UNL ARMISS_stru::ADC(){ long rst,a,b,op; bit32_stru b1,b2,b3; a = oper; b = shifter.operand; rst = a + b + CPSR.C; if( ( update_flags ) && ( des_reg == 15 ) ) CPSR = SPSR[getid()]; else if( update_flags ) { b1 = a; b2 = b; b3 = rst; op = b1[31]; op = (op << 1) + b2[31]; op = (op << 1) + b3[31]; CPSR.N = b3[31]; CPSR.Z = rst == 0? 1:0; switch( op ) { case 1 : CPSR.C = CPSR.V = 1; break; case 2 : case 3 : case 4 : case 5 : CPSR.C = ( b1 + b2 ); CPSR.V = 0; break; case 6 : CPSR.C = CPSR.V = 1; break; case 7 : CPSR.C = ( b1 + b2 ); CPSR.V = 0; break; } } return rst; }UNL ARMISS_stru::SBC(){ long rst,a,b; bit32_stru b1,b2,b3; int op; a = oper; b = shifter.operand; rst = a - b -!CPSR.C ; if( ( update_flags ) && ( des_reg == 15 ) ) CPSR = SPSR[getid()]; else if ( update_flags ) { b1 = a; b2 = (-1)*b; b3 = rst; CPSR.N = b3[31]; CPSR.Z = ( rst == 0 )? 1 : 0; op = b1[31]; op = op << 1; op = op + b2[31]; op=op<<1;op=op+b3[31]; if( b == 0 ) { CPSR.C = 1; CPSR.V = 0; } else switch( op ) { case 0 : CPSR.C = 0; CPSR.V = 0; break; case 1 : CPSR.C = 0; CPSR.V = 1; break; case 2 : CPSR.C = 1; CPSR.V = 0; break; case 3 : CPSR.C = CPSR.V = 0; break; case 4 : CPSR.C = 1; CPSR.V = 0; break; case 5 : CPSR.C = CPSR.V = 0; break; case 6 : CPSR.C = CPSR.V = 1; break; case 7 : CPSR.C = 1; CPSR.V = 0; break; } } return ( rst );}UNL ARMISS_stru::RSC(){ long rst,a,b; bit32_stru b1,b2,b3; int op; b = oper; a = shifter.operand; rst = a - b - !CPSR.C; if( ( update_flags ) && ( des_reg == 15 ) ) CPSR = SPSR[getid()]; else if ( update_flags ) { b1 = a; b2 = (-1)*b; b3 = rst; CPSR.N = b3[31]; CPSR.Z = ( rst == 0 )? 1 : 0; op = b1[31]; op = op << 1; op = op + b2[31]; op=op<<1;op=op+b3[31]; if( b == 0 ) { CPSR.C = 1; CPSR.V = 0;} else switch( op ) { case 0 : CPSR.C = 0; CPSR.V = 0; break; case 1 : CPSR.C = 0; CPSR.V = 1; break; case 2 : CPSR.C = 1; CPSR.V = 0; break; case 3 : CPSR.C = CPSR.V = 0; break; case 4 : CPSR.C = 1; CPSR.V = 0; break; case 5 : CPSR.C = CPSR.V = 0; break; case 6 : CPSR.C = CPSR.V = 1; break; case 7 : CPSR.C = 1; CPSR.V = 0; break; } } return ( rst ); }void ARMISS_stru::TST(){ long tmp; tmp = oper & shifter.operand ; CPSR.N = tmp >> 31; CPSR.Z = (tmp == 0)? 1:0; CPSR.C = shifter.carry_out;}void ARMISS_stru::TEQ(){ long tmp; tmp = oper ^ shifter.operand ; CPSR.N = tmp >> 31; CPSR.Z = (tmp == 0)? 1:0; CPSR.C = shifter.carry_out;}void ARMISS_stru::CMP(){ long a; long b,tmp; bit32_stru b1,b2,b3; int op; a = oper; b = shifter.operand; tmp = a - b ; b1 = a; b2 = (-1)*b; b3 = tmp; CPSR.N = b3[31]; CPSR.Z = ( tmp == 0 )? 1 : 0; op = b1[31]; op = op << 1; op = op + b2[31]; op=op<<1;op=op+b3[31]; if( b == 0 ) { CPSR.C = 1;CPSR.V = 0;} else switch( op ) { case 0 : CPSR.C = 0; CPSR.V = 0; break; case 1 : CPSR.C = 0; CPSR.V = 1; break; case 2 : CPSR.C = 1; CPSR.V = 0; break; case 3 : CPSR.C = CPSR.V = 0; break; case 4 : CPSR.C = 1; CPSR.V = 0; break; case 5 : CPSR.C = CPSR.V = 0; break; case 6 : CPSR.C = CPSR.V = 1; break; case 7 : CPSR.C = 1; CPSR.V = 0; break; } }void ARMISS_stru::CMN(){ long a,b,tmp; bit32_stru b1,b2,b3; int op; a = oper; b = shifter.operand; tmp = a + b; CPSR.N = tmp >> 31; CPSR.Z = (tmp == 0) ? 1:0; b1 = a; b2 = b; b3 = tmp; op = b1[31]; op = op << 1; op = op + b2[31];op=op<<1;op=op+b3[31]; switch( op ) { case 1 : CPSR.C = CPSR.V = 1; break; case 2 : case 3 : case 4 : case 5 : CPSR.C = ( b1 + b2 ); CPSR.V = 0; break; case 6 : CPSR.C = CPSR.V = 1; break; case 7 : CPSR.C = ( b1 + b2 ); CPSR.V = 0; break; } }UNL ARMISS_stru::ORR(){ long rst; rst = oper | shifter.operand ; if( ( update_flags ) && ( des_reg == 15 ) ) CPSR = SPSR[getid()]; else if ( update_flags ) { CPSR.N = rst >> 31; CPSR.Z = ( rst == 0 )? 1 : 0; CPSR.C = shifter.carry_out; } return ( rst );}UNL ARMISS_stru::MOV(){ long rst; rst = shifter.operand ; if( ( update_flags ) && ( des_reg == 15 ) ) { if( getid() != -1 ) CPSR = SPSR[getid()]; } else if ( update_flags ) { CPSR.N = rst >> 31; CPSR.Z = ( rst == 0 )? 1 : 0; CPSR.C = shifter.carry_out; } return ( rst ); }UNL ARMISS_stru::BIC(){ long rst; rst = oper & ( ~shifter.operand ); ; if( ( update_flags ) && ( des_reg == 15 ) ) CPSR = SPSR[getid()]; else if ( update_flags ) { CPSR.N = rst >> 31; CPSR.Z = ( rst == 0 )? 1 : 0; CPSR.C = shifter.carry_out; } return ( rst ); }UNL ARMISS_stru::MVN(){ long rst; rst = ~shifter.operand ; if( ( update_flags ) && ( des_reg == 15 ) ) CPSR = SPSR[getid()]; else if ( update_flags ) { CPSR.N = rst >> 31; CPSR.Z = ( rst == 0 )? 1 : 0; CPSR.C = shifter.carry_out; } return ( rst );}CPSR_stru ARMISS_stru::MRS(){ ARM_type0_stru& tmp = ARM_type0; if( tmp.mis.R == 1 ) return SPSR[getid()]; else return CPSR;} void ARMISS_stru::MSR(){ ARM_type0_stru& tmp = ARM_type0; long t; if( tmp.mis.R == 0 ) { t = CPSR; if( ((tmp.mis.mask & 0x1) == 1) && (CPSR.M > 16) ) { t = t & 0xffffff00; t = t | (oper & 0xff); } if( ((tmp.mis.mask & 0x2) > 0) && (CPSR.M > 16) ) { t = t & 0xffff00ff; t = t | (oper & 0xff00); } if( ((tmp.mis.mask & 0x4) > 0) && (CPSR.M > 16) ) { t = t & 0xff00ffff; t = t | (oper & 0xff0000); } if( ((tmp.mis.mask & 0x8) > 0) && (CPSR.M > 16) ) { t = t & 0xff000000; t = t | (oper & 0xff000000); } CPSR = t; } else { if( (CPSR.M > 16) && (CPSR.C < 31) )⌨️ 快捷键说明
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