armcommon_iacxl10_2004_3_16.cpp

自己编写的ARM处理器的指令集仿真

    
  offset_8 = (tmp.mul_ext.Hioffset << 4) | tmp.mul_ext.Loffset;
  op       = (tmp.mul_ext.P<<2) + (tmp.mul_ext.b22<<1) + tmp.mul_ext.W;
  rm       = (tmp.mul_ext.Rm==PC)? getregd( tmp.mul_ext.Rm )+8 : getregd( tmp.mul_ext.Rm);
  trn       = (tmp.mul_ext.Rn2==PC)?getregd(tmp.mul_ext.Rn2)+8:getregd(tmp.mul_ext.Rn2);

  switch( op )
 {
   case  0  : addr = trn;
              if( executable() )
              {
               rn = tmp.mul_ext.U2==1?(rn+rm):(rn+rm);
               if( tmp.mul_ext.Rn2==PC) pc_changed=true;
              }
              break;
   case  2  : addr = trn;
              if( executable() )
              {  rn = (tmp.mul_ext.U2==1)?(rn+offset_8):(rn-offset_8);
                 if( tmp.mul_ext.Rn2==PC) pc_changed=true;
              }
              break;
   case  4  : addr =(tmp.mul_ext.U2==1)?(trn+rm):(trn-rm);
              break;
   case  5  : addr=(tmp.mul_ext.U2==1)?(trn+rm):(trn-rm);
              if( executable() )
              {
                 rn = addr;
                 pc_changed=(tmp.mul_ext.Rn2==PC)?true:false;
              }
              break;
   case  6  : addr = (tmp.mul_ext.U2==1)? (trn+offset_8):(trn-offset_8);
              break;
   case  7  : addr = (tmp.mul_ext.U2==1)? (trn+offset_8):(trn-offset_8);
              if( executable() )
              {
                  rn = addr;
                  pc_changed = (tmp.mul_ext.Rn2==PC)?true:false;
              }
              break;
  }
   
 return addr;  
      
}//Miscellaneous Loads and Stores;
  





UNL ARMISS_stru::addr_mod2_shift(int mod,int mount,UNL oper)
{
      bit32_stru   bit;
      UNL          rst;

      bit = oper;

      switch( mod )
      {
         case 0: rst = oper << mount;
                 break;
         case 1: if( mount == 0 )
                       rst = 0;
                 else
                       rst = (unsigned)oper >> mount;
                 break;
         case 2: if( mount == 0 )
                    if( (oper & 0x80000000) == 0 )
                                 rst = 0;
                    else
                                 rst = 0xffffffff;
                 else
                       rst = oper >> mount;
                 break;
         case 3: if( mount == 0 )
                       rst = CPSR.C || ( (unsigned)oper >> 1 );
                 else
                       {
                           bit.rotate( mount );
                           rst = bit;
                       }
                 break;
        default: rst = oper;
                 break;
      }

      return rst;
}                             

addr_stru ARMISS_stru::Addressing_mod4()
{
     ARM_type4_stru&   tmp = ARM_type4;
     UNL               rn  = getregd(tmp.Rn);
     UNL&              rt  = getreg( tmp.Rn );
     addr_stru         rst;
     int               op;

     if( (tmp.Rn == 15) ) rn = rn + 8;
     op = tmp.P; 
     op = (op << 1) + tmp.U;

     switch( op )
     {
       case 0 : rst.start = rn - count1( tmp.reg_list )*4 + 4;
                rst.end   = rn;
                if( tmp.W == 1 )
                    rt = rt - count1( tmp.reg_list )*4;
                break;
       case 1 : rst.start = rn;
                rst.end   = rn + count1( tmp.reg_list )*4 - 4;
                if( tmp.W == 1 )
                         rt = rt + count1( tmp.reg_list )*4;
                break;
      case  2 : rst.start = rn - count1( tmp.reg_list )*4;
                rst.end   = rn - 4;
                if( tmp.W == 1 )
                     rt = rt - count1( tmp.reg_list )*4;
                break;
      case  3 : rst.start = rn + 4;
                rst.end   = rn + count1( tmp.reg_list )*4;
                if( tmp.W == 1 )
                        rt = rt + count1( tmp.reg_list )*4;
                break;
      default:  rst.start = 0;
                rst.end   = 0;
                break;
    }
    if( (tmp.W == 1) && (tmp.Rn == 15) ) pc_changed = true; 
   
    return rst;
}//Load and Store Mutiple;


addr_stru ARMISS_stru::Addressing_mod5()
{
  /* ARM_type6_stru&   tmp = ARM_type6;
   addr_stru         rst;
   UNL&              Rn  = getreg( tmp.Rn );
   UNL               offset8,op,r;

   op = tmp.P; op = op << 1; op = op + tmp.W;
   offset8 = tmp.offset;
   r  = getregd( tmp.Rn );if( tmp.Rn == PC ) r = r + 8;
   switch( op )
  {
     case 0 : rst.start = (tmp.Rn == PC )? Rn+8:Rn;
              rst.end   = rst.start + tmp.N*60;
              break;
     case 1 : rst.start = (tmp.Rn == PC )? Rn+8:Rn;
              rst.end   = rst.start + tmp.N*60;
              Rn        = Rn - ((-1)*tmp.U)*offset8*4;
              if( tmp.Rn == PC ) 
                pc_changed = true; 
              break;
     case 2 : rst.start = r - ((-1)*tmp.U)*offset8*4;
              rst.end   = rst.start + tmp.N*60;
              break;
     case 3 : Rn        = Rn - ((-1)*tmp.U)*offset8*4;
              rst.start = r;
              rst.end   = rst.start + tmp.N*60;
              if( tmp.Rn == PC ) 
                pc_changed = true; 
              break;
     default: break;
  }
   
   return rst;
*/
}    

bool ARMISS_stru::executable()
{
   
       switch( common_dec.flags )
         {
              case  0: return CPSR.Z ;
                      
              case  1: return !CPSR.Z;
                      
              case  2: return  CPSR.C;
                       
              case  3: return  !CPSR.C ;
                      
              case  4: return  CPSR.N;
                       
              case  5: return  !CPSR.N;
                       
              case  6: return  CPSR.V;
                       
              case  7: return  !CPSR.V;
                       
              case  8: return (CPSR.C && !CPSR.Z); 
                            
              case  9: return ( !CPSR.C || CPSR.Z );
    
              case 10: return ( CPSR.N == CPSR.V );

              case 11: return ( CPSR.N != CPSR.V );

              case 12: return ( !CPSR.Z && (CPSR.N == CPSR.V) );

              case 13: return ( CPSR.Z || ( CPSR.N != CPSR.V ) );

              case 14: return true;
                            
              case 15: return true;
          }
}//This function is called by executable to determine wether the instruct can be executed or not;



void ARMISS_stru::prefetch_abt_handle()
{
      long        t;
      bit32_stru  bit;
    
      r_abt[1]  = r_gen[PC];
      SPSR[abt] = CPSR;
      t         = CPSR;
      bit       = t;
      bit[0]    = 1;
      bit[1]    = 1;
      bit[2]    = 1;
      bit[3]    = 0;
      bit[4]    = 1;
      bit[5]    = 0;
      bit[7]    = 1;
      t         = bit;
      CPSR      = t;
      r_gen[PC] = 0xc;
}//Prefetch abort handle;



void ARMISS_stru::undef_abt_handle()
{
     long       t;
     bit32_stru bit;

     r_und[1]  = r_gen[PC];
     SPSR[und] = CPSR;
     t         = CPSR;
     bit       = t;
     bit[0]    = 1;
     bit[1]    = 1;
     bit[2]    = 0;
     bit[3]    = 1;
     bit[4]    = 1;
     bit[5]    = 0;
     bit[7]    = 1;
     CPSR      = bit;
 
     r_gen[PC] = 0x4;
}//Undefined abort handle;

void ARMISS_stru::data_abt_handle()
{
    long       t;
    bit32_stru bit;

    r_abt[1]   = r_gen[PC];
    SPSR[abt]  = CPSR;
    t          = CPSR;
    bit        = t;
    bit[0]     = 1;
    bit[1]     = 1;
    bit[2]     = 1;
    bit[3]     = 0;
    bit[4]     = 1;
    bit[5]     = 0;
    bit[7]     = 1;
    CPSR       = bit;
 
    r_gen[PC]  = 0x10;
}//Data abort handle;

void ARMISS_stru::irq_ext_handle()
{
    long       t;
    bit32_stru bit;

  if( pc_changed )
    r_irq[1]  = r_gen[PC] + 4;
  else 
    r_irq[1]  = r_gen[PC] + 8;
    SPSR[irq] = CPSR;
    t         = CPSR;
    bit       = t;
    bit[0]    = 0;
    bit[1]    = 1;
    bit[2]    = 0;
    bit[3]    = 0;
    bit[4]    = 1;
    bit[5]    = 0;
    bit[7]    = 1;
    CPSR      = bit;
    r_gen[PC] = 0x18;
}//Normal interrupt handle;

void ARMISS_stru::fiq_ext_handle()
{
   long       t;
   bit32_stru bit;
 
   r_fiq[6]  = CPSR;
   SPSR[fiq] = CPSR;
   t         = CPSR;
   bit       = t;
   bit[4]    = 1;
   bit[3]    = 0;
   bit[2]    = 0;
   bit[1]    = 0;
   bit[0]    = 1;
   bit[5]    = 0;
   bit[6]    = 1;
   bit[7]    = 1;
   CPSR      = bit;

   r_gen[PC] = 0x1c;
}//Normal interrupt handle;
  
  
ARMISS_stru::ARMISS_stru()
{
      for( int i=0; i<16; i++ )
          r_gen[i] = 0;
      fiq_pt = false;
      irq_pt = false;
}


UNL ARMISS_stru::rotate_shift(UNL oper,int mount)
{
      bit32_stru   bit;
      UNL          rst;

      bit = oper;
      bit.rotate( mount );
      rst = bit;
      return rst;      
}

void ARMISS_stru::irq_reg(IRQFUN ptr)
{
      pirq   = ptr;
      irq_pt = true;
}//Normal interrupt function register; 

void ARMISS_stru::fiq_reg(FIQFUN ptr)
{
     pfiq   = ptr;
     fiq_pt = true;
}//Fast interrupt function register;


void ARMISS_stru::copro_reg(COPROFUN ptr)
{
     pcopro   = ptr;
     copro_pt = true;
}//coprocessor function register;

int ARMISS_stru::check_except()
{
   if( data_abt ) //数据访存异常；
    {
         data_abt_handle();
         data_abt = false;
         return 0;
    }
    if( fiq_ext ) //快中断；
    {
         fiq_ext_handle();
         fiq_ext = false;
         return 0;
    }
    if( irq_ext )//中断；
    {
         irq_ext_handle();
         irq_ext = false;
         return 0;
    }
    if( prefetch_abt )//预取指异常;
    {
         prefetch_abt_handle();
         prefetch_abt = false;
         return 0;
    }
    if( undef_abt )//未定义指令异常；
    {
         undef_abt_handle();
         undef_abt = false;
         return 0;
    } 

   
    return 1;

}//Check if a interrupt or abort happend;