at91_mygpio.h

gpio driver for atmel ar91rm92

/*======================================================================
	current file::/drivers/at91/at91_mygpio.h
	Device driver for the GPIO(PIO) control of Atmel AT91RM9200
	(c)e-tek Ltd,Shenzhen,Guangdong,China

	The original code is created by beeswing<[e-mail]>. 
	Copyright (C) 2005 beeswing.  
	All Rights Reserved.    
======================================================================*/ 

#ifndef __AT91RM9200_GPIO_H
#define __AT91RM9200_GPIO_H

#include <asm/sizes.h>

#include <asm/arch/AT91RM9200.h>
#include <asm/arch/AT91RM9200_SYS.h>

#define AT91C_BASE_PIOA		(0xFFFFF400) // PIOA Base Address
#define AT91C_BASE_PIOB		(0xFFFFF600) // PIOB Base Address
#define AT91C_BASE_PIOC		(0xFFFFF800) // PIOC Base Address
#define AT91C_BASE_PIOD		(0xFFFFFA00) // PIOD Base Address

#define PIO_PORTA	0
#define PIO_PORTB	1
#define PIO_PORTC	2
#define PIO_PORTD	3

#ifndef _IO(x,y)
#define _IO(x,y)	(((x)<<8)|y)
#endif

#define	GPIO_IOCTL_BASES		'g'	// 0x67 from ioctl list

//Gpio function select
#define PIO_SET_GPIO		_IO(GPIO_IOCTL_BASES, 0)

//Peripheral A select
#define PIO_SET_PASR		_IO(GPIO_IOCTL_BASES, 1)

//Peripheral B select
#define PIO_SET_PBSR		_IO(GPIO_IOCTL_BASES, 2)


//direction
#define PIO_SET_INPUT		_IO(GPIO_IOCTL_BASES, 4)
#define PIO_SET_OUTPUT		_IO(GPIO_IOCTL_BASES, 5)


#ifndef GPIO_MAJOR
#define GPIO_MAJOR 61
#endif
#define NR_GPIO_DEVICES	 3
#define PIO_GPIO(Num)	(0x00000001 << Num)

#ifdef	BOARD_4_DEBUG
	#define	PORTS_NUM	4
#else
	#define	PORTS_NUM	3
#endif

typedef struct _AT91S_PIO {
	AT91_REG	 PIO_PER; 	// PIO Enable Register
	AT91_REG	 PIO_PDR; 	// PIO Disable Register
	AT91_REG	 PIO_PSR; 	// PIO Status Register
	AT91_REG	 Reserved0; 	//
	AT91_REG	 PIO_OER; 	// Output Enable Register
	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
	AT91_REG	 PIO_OSR; 	// Output Status Register
	AT91_REG	 Reserved1; 	//
	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
	AT91_REG	 Reserved2; 	//
	AT91_REG	 PIO_SODR; 	// Set Output Data Register
	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
	AT91_REG	 Reserved3; 	//
	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
	AT91_REG	 PIO_PPUSR; 	// Pad Pull-up Status Register
	AT91_REG	 Reserved4; 	//
	AT91_REG	 PIO_ASR; 	// Select A Register
	AT91_REG	 PIO_BSR; 	// Select B Register
	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
	AT91_REG	 Reserved5[9]; 	//
	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;

#endif