test.v

来自「一个关于DES算法的verilog语言实现,包括了各个实现模块以及测试模块」· Verilog 代码 · 共 26 行

module  vdestest;
reg     dec;
reg		clk;
wire	[63:0]	desOut;
wire	[63:0]	desIn;
wire	[55:0]	vkey;

assign  #1 vkey =56'b01010101011100011111010101101;
assign  #1 desIn =64'001011111000110010011000010110111101101111110100
    0110101100011110;
always #100 clk=~clk;
	
initial
      begin 
clk=0;	
dec=1;
      end
   
vdes vdes1(.desOut( desOut ),
             .desIn( desIn ),	
             .vkey( vkey ), 
		      .dec( dec ),
             .clk( clk )			 
              );		
endmodule