pcicfg.cpp

这是运行在windows ce 4.2 版本下的关于硬盘加载的驱动程序

            Offset += 4;
            i++;
            PCIConfig_Write(Bus, Device, Function, Offset, 0x0);
        }
    }

    //
    // Add resource for expansion ROM, offset 0x30
    //
    Offset = 0x30;
    PCIConfig_Write(Bus, Device, Function, Offset ,0xFFFFFFFF);
    BaseAddress = PCIConfig_Read(Bus, Device, Function, Offset);
   
    // Memory space
    Size = ~(BaseAddress & 0xFFFFFFF0);
    Reg &= 0xFFFFFFF0;
        
    // Check that the register has a valid format; it should have consecutive high 1's and consecutive low 0's
    SizeFound = (BaseAddress != 0) && (BaseAddress != 0xFFFFFFFF) && (((Size + 1) & Size) == 0);

    Size +=1;

    if (SizeFound) {
        PPCI_RSRC Rsrc = PCIRsrc_New(Bus, Device, Function, Offset, Reg, Size, FALSE, 0, FALSE, pInfo->ConfigInfo);

        if (!Rsrc) {
            DEBUGMSG(ZONE_PCI | ZONE_ERROR, (L"ATAPI:PCIConfig!ConfigRsrc: Failed local alloc of Rsrc\r\n"));
            return FALSE;
        }

        *pMemSize += Size;
        PCIRsrc_Add(pMemHead, Rsrc);


        DEBUGMSG(ZONE_PCI | ZONE_INIT, (L"ATAPI:PCIConfig!ConfigRsrc: ROM(%d/%d/%d): Offset 0x%x, Type Memory, Size 0x%X\r\n",
            Bus, Device, Function, Offset, Size));
    }
    
    DEBUGMSG(ZONE_PCI | ZONE_INIT, (L"ATAPI:PCIConfig!ConfigRsrc-\r\n", Bus, Device, Function));

    return TRUE;
}


//
// ConfigSize
//
static BOOL ConfigSize(
    PPCI_DEV_INFO pInfo 
    )
{
    DWORD NumberOfRegs;
    DWORD Offset;
    DWORD i;
    DWORD BaseAddress;
    DWORD Size;
    DWORD Reg;
    DWORD IoIndex = 0;
    DWORD MemIndex = 0;

    DEBUGMSG(ZONE_INIT | ZONE_PCI, (L"ATAPI:PCIConfig!ConfigSize+(Bus %d, Device %d, Function %d)\r\n",
        pInfo->Bus, pInfo->Device, pInfo->Function));

    // Determine number of BARs to examine from header type
    switch (pInfo->Cfg->HeaderType & ~PCI_MULTIFUNCTION) {
    case PCI_DEVICE_TYPE:
        NumberOfRegs = PCI_TYPE0_ADDRESSES;
        break;

    case PCI_BRIDGE_TYPE:
        NumberOfRegs = PCI_TYPE1_ADDRESSES;
        break;

    case PCI_CARDBUS_TYPE:
        NumberOfRegs = PCI_TYPE2_ADDRESSES;
        break;

    default:
        return FALSE;
    }
        
    for (i = 0, Offset = 0x10; i < NumberOfRegs; i++, Offset += 4) {
        // Get base address register value
        Reg = pInfo->Cfg->u.type0.BaseAddresses[i];

        // Legacy I/O
        if (i <= 3) {
            switch(i) {
                case 0:
                    if (!Reg) 
                        Reg = 0x1F1;
                    Size = 0x8;
                    break;
                case 1:
                    if (!Reg)
                        Reg = 0x3F5;
                    Size = 0x4;
                    break;
                case 2:
                    if (!Reg)
                        Reg = 0x171;
                    Size = 0x8;
                    break;
                case 3:
                    if (!Reg)
                        Reg = 0x375;
                    Size = 0x4;
                    break;
            }           
            
            pInfo->IoLen.Reg[IoIndex] = Size;
            pInfo->IoLen.Num++;
            pInfo->IoBase.Reg[IoIndex++] = Reg & PCI_ADDRESS_IO_ADDRESS_MASK;
            pInfo->IoBase.Num++;
        } else {
            // Get size info
            PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, Offset, 0xFFFFFFFF);
            BaseAddress = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, Offset);
            PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, Offset, Reg);
    
            if (Reg & PCI_ADDRESS_IO_SPACE) {
                // IO space
                // Re-adjust BaseAddress if upper 16-bits are 0 (this is allowable in PCI 2.2 spec)
                if (((BaseAddress & PCI_ADDRESS_IO_ADDRESS_MASK) != 0) && ((BaseAddress & 0xFFFF0000) == 0)) {
                    BaseAddress |= 0xFFFF0000;
                }
                
                Size = ~(BaseAddress & PCI_ADDRESS_IO_ADDRESS_MASK);
    
                if ((BaseAddress != 0) && (BaseAddress != 0xFFFFFFFF) && (((Size + 1) & Size) == 0)) {
                    // BAR has valid format (consecutive high 1's and consecutive low 0's)
                    pInfo->IoLen.Reg[IoIndex] = Size + 1;
                    pInfo->IoLen.Num++;
                    pInfo->IoBase.Reg[IoIndex++] = Reg & PCI_ADDRESS_IO_ADDRESS_MASK;
                    pInfo->IoBase.Num++;
                } else {
                    // BAR invalid => skip to next one
                    continue;
                }
            } else {
                // Memory space
                if ((Reg & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT) {
                    // PCI 2.2 spec no longer supports this type of memory addressing
                    DEBUGMSG(ZONE_ERROR, (L"ATAPI:PCIConfig!ConfigSize: 20-bit addressing not supported\r\n"));
                    return FALSE;
                }
                
                // Re-adjust BaseAddress if upper 16-bits are 0 (this is allowable in PCI 2.2 spec)
                if (((BaseAddress & PCI_ADDRESS_MEMORY_ADDRESS_MASK) != 0) && ((BaseAddress & 0xFFFF0000) == 0)) {
                    BaseAddress |= 0xFFFF0000;
                }
                
                Size = ~(BaseAddress & PCI_ADDRESS_MEMORY_ADDRESS_MASK);
    
                if ((BaseAddress != 0) && (BaseAddress != 0xFFFFFFFF) && (((Size + 1) & Size) == 0)) {
                    // BAR has valid format (consecutive high 1's and consecutive low 0's)
                    pInfo->MemLen.Reg[MemIndex] = Size + 1;
                    pInfo->MemLen.Num++;
                    pInfo->MemBase.Reg[MemIndex++] = Reg & PCI_ADDRESS_MEMORY_ADDRESS_MASK;
                    pInfo->MemBase.Num++;
                } else {
                    // BAR invalid => skip to next one
                    continue;
                }
    
                if ((Reg & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT) {
                    // 64 bit device - BAR is twice as wide, skip upper 32-bits
                    Offset += 4;
                    i++;
                }
            }
        }
    }

    DEBUGMSG(ZONE_INIT | ZONE_PCI, (L"ATAPI:PCIConfig!ConfigSize-\r\n"));

    return TRUE;
}


//
// ConfigInit
//
static BOOL ConfigInit(
    PPCI_DEV_INFO pInfo 
    )
{
    return TRUE;
}

//
// PromiseInit
//
static BOOL PromiseInit(
    PPCI_DEV_INFO pInfo 
    )
{
    DWORD dwInfo;
    dwInfo = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x60);
    DEBUGMSG( ZONE_INIT, (L"ATAPI:PromiseInit Value at offset 0x60 is %08X\r\n", dwInfo));
    dwInfo = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x64);
    DEBUGMSG( ZONE_INIT, (L"ATAPI:PromiseInit Value at offset 0x64 is %08X\r\n", dwInfo));
    dwInfo = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x68);
    DEBUGMSG( ZONE_INIT, (L"ATAPI:PromiseInit Value at offset 0x68 is %08X\r\n", dwInfo));
    dwInfo = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x6C);
    DEBUGMSG( ZONE_INIT, (L"ATAPI:PromiseInit Value at offset 0x6C is %08X\r\n", dwInfo));
    PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, 0x60, 0x004FF304);
    PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, 0x64, 0x004FF304);
    PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, 0x68, 0x004FF304);
    PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, 0x6C, 0x004FF304);
    dwInfo = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x60);
    DEBUGMSG( ZONE_INIT, (L"ATAPI:PromiseInit Value at offset 0x60 is %08X\r\n", dwInfo));
    dwInfo = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x64);
    DEBUGMSG( ZONE_INIT, (L"ATAPI:PromiseInit Value at offset 0x64 is %08X\r\n", dwInfo));
    dwInfo = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x68);
    DEBUGMSG( ZONE_INIT, (L"ATAPI:PromiseInit Value at offset 0x68 is %08X\r\n", dwInfo));
    dwInfo = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x6C);
    DEBUGMSG( ZONE_INIT, (L"ATAPI:PromiseInit Value at offset 0x6C is %08X\r\n", dwInfo));
     return TRUE;
}

//
// DeviceConfig
//
EXTERN_C BOOL PromiseConfig(
    DWORD Command, 
    PPCI_DEV_INFO pInfo,
    PPCI_RSRC pRsrc1,
    PPCI_RSRC pRsrc2,
    DWORD *pMemSize,
    DWORD *pIoSize
    )
{
    DEBUGMSG(1, (L"ATAPI:PCIConfig!DeviceConfig+(%d)\r\n", Command));

    switch (Command) {
    case PCIBUS_CONFIG_RSRC:
        return ERROR_NOT_SUPPORTED;

    case PCIBUS_CONFIG_SET:
        return ERROR_NOT_SUPPORTED;
        
    case PCIBUS_CONFIG_SIZE:
        return ERROR_NOT_SUPPORTED;

    case PCIBUS_CONFIG_INIT:
        if (PromiseInit(pInfo)) {
            return ERROR_SUCCESS;
        } else {
            return ERROR_GEN_FAILURE;
        }

    default:
        break;
    }

    DEBUGMSG(1, (L"ATAPI:PCIConfig!DeviceConfig-: ERROR: Command %d not recognized\r\n", Command));
    
    return ERROR_BAD_COMMAND;
}



/*
0x83fde63c: ATAPI:AliInit Value at offset 00 is 522910B9
0x83fde63c: ATAPI:AliInit Value at offset 04 is 02800005
0x83fde63c: ATAPI:AliInit Value at offset 08 is 01018AC1
0x83fde63c: ATAPI:AliInit Value at offset 0C is 00002000
0x83fde63c: ATAPI:AliInit Value at offset 10 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 14 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 18 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 1C is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 20 is 0000D001
0x83fde63c: ATAPI:AliInit Value at offset 24 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 28 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 2C is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 30 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 34 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 38 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 3C is 04020100
0x83fde63c: ATAPI:AliInit Value at offset 40 is 7A000000
0x83fde63c: ATAPI:AliInit Value at offset 44 is 00000000
0x83fde63c: ATAPI:AliInit Value at offset 48 is 4A000000
0x83fde63c: ATAPI:AliInit Value at offset 4C is 3ABA8000
0x83fde63c: ATAPI:AliInit Value at offset 50 is 89000001
0x83fde63c: ATAPI:AliInit Value at offset 54 is 77777777
0x83fde63c: ATAPI:AliInit Value at offset 58 is 00310000
*/

static BOOL AliInit(
    PPCI_DEV_INFO pInfo 
    )
{
    DWORD dwIndex, dwValue;
    
    for (dwIndex=0; dwIndex <= 0x5A; dwIndex += 4) {
        dwValue = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, dwIndex);
        DEBUGMSG( ZONE_INIT, (L"ATAPI:AliInit Value at offset %02X is %08X\r\n", dwIndex, dwValue));
    }
    DEBUGMSG( ZONE_INIT, (L"\r\n"));
    DEBUGMSG( ZONE_INIT, (L"\r\n"));
    DEBUGMSG( ZONE_INIT, (L"\r\n"));

    
    dwValue = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x50);
    dwValue |= 0x01000001;
    PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, 0x50, dwValue);

    dwValue = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x54);
    dwValue = 0x77777777;
    PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, 0x54, dwValue);
    
    dwValue = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, 0x58);
    dwValue = 0x00000000;
    PCIConfig_Write(pInfo->Bus, pInfo->Device, pInfo->Function, 0x58, dwValue);
    
    for (dwIndex=0; dwIndex <= 0x5A; dwIndex += 4) {
        dwValue = PCIConfig_Read(pInfo->Bus, pInfo->Device, pInfo->Function, dwIndex);
        DEBUGMSG( ZONE_INIT, (L"ATAPI:AliInit Value at offset %02X is %08X\r\n", dwIndex, dwValue));
    }
    return TRUE;
}


EXTERN_C BOOL AliConfig(
    DWORD Command, 
    PPCI_DEV_INFO pInfo,
    PPCI_RSRC pRsrc1,
    PPCI_RSRC pRsrc2,
    DWORD *pMemSize,
    DWORD *pIoSize
    )
{
    DEBUGMSG(1, (L"ATAPI:PCIConfig!DeviceConfig+(%d)\r\n", Command));
    
    switch (Command) {
    case PCIBUS_CONFIG_RSRC:
        if (ConfigRsrc(pInfo, pRsrc1, pRsrc2, pMemSize, pIoSize)) {
            return ERROR_SUCCESS;
        } else {
            return ERROR_GEN_FAILURE;
        }

    case PCIBUS_CONFIG_SET:
        return ERROR_NOT_SUPPORTED;
        
    case PCIBUS_CONFIG_SIZE:
        if (ConfigSize(pInfo)) {
            return ERROR_SUCCESS;
        } else {
            return ERROR_GEN_FAILURE;
        }

    case PCIBUS_CONFIG_INIT:
        if (AliInit(pInfo)) {
            return ERROR_SUCCESS;
        } else {
            return ERROR_GEN_FAILURE;
        }

    default:
        break;
    }

    DEBUGMSG(1, (L"ATAPI:PCIConfig!DeviceConfig-: ERROR: Command %d not recognized\r\n", Command));
    
    return ERROR_BAD_COMMAND;
}