atapi2.h

这是运行在windows ce 4.2 版本下的关于硬盘加载的驱动程序

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  

    atapi.h

Abstract:

    This module contains the function prototypes and constant, type and
    structure definitions for the WINCE Implementation of the AT
    Attachment API for disk devices.

Notes: 


--*/

#ifndef _ATAPI_H_
#define _ATAPI_H_

#define BYTES_PER_SECTOR        512
#define CDROM_RAW_SECTOR_SIZE   2352
#define CDROM_SECTOR_SIZE       2048

#define ATA_MEM_REG_BASE    (0<<1)    
#define ATA_REG_DATA        (0<<1)
#define ATA_REG_FEATURE     (1<<1)   // write
#define ATA_REG_ERROR       (1<<1)   // read
#define ATA_REG_SECT_CNT    (2<<1)
#define ATA_REG_SECT_NUM    (3<<1)
#define ATA_REG_CYL_LOW     (4<<1)
#define ATA_REG_CYL_HIGH    (5<<1)
#define ATA_REG_DRV_HEAD    (6<<1)
#define ATA_REG_COMMAND     (7<<1)   // write
#define ATA_REG_STATUS      (7<<1)   // read     (reading this acknowledges the interrupt)
#define ATA_REG_LENGTH      ATA_REG_STATUS+2

#define ATA_REG_BYTECOUNTLOW    ATA_REG_CYL_LOW    
#define ATA_REG_BYTECOUNTHIGH   ATA_REG_CYL_HIGH
#define ATA_REG_REASON          2


// CMD PCI chip maps four bytes starting at 3f4

#define ATA_REG_ALT_STATUS  0   // read     (reading this does not ack the interrupt)
#define ATA_REG_DRV_CTRL    0   // write

#define ATA_ALT_MEM_REG_BASE               (ATA_MEM_REG_BASE + 0x800000 + (6<<1))
#define ATA_ALT_REG_LENGTH                  4

//
// ATA drive select/head register bit masks.
//
#define ATA_HEAD_MUST_BE_ON         0xA0 // These 2 bits are always on
#define ATA_HEAD_DRIVE_1            (0x00 | ATA_HEAD_MUST_BE_ON)
#define ATA_HEAD_DRIVE_2            (0x10 | ATA_HEAD_MUST_BE_ON)
#define ATA_HEAD_LBA_MODE           (0x40 | ATA_HEAD_MUST_BE_ON)

//
// ATAPI Interrupt Reason (ATA Sector Count) Definition
//
#define ATA_IR_CoD          0x01    // Command OR Data
#define ATA_IR_IO           0x02    // Input OR Output (Host & Device)
#define ATA_RELEASED        0x04    // ATA Bus Released


//
//  ATAPI Interrupt Reason & Status Reg. Results
//
//                                 DRQ-IO-CoD
#define ATA_INTR_CMD    5       //   1- 0 - 1 (5) ATA Device acknowledge command
#define ATA_INTR_MSG    7       //   1- 1 - 1 (7) ATA Device ready to send MSG (Future) to host
#define ATA_INTR_READ   6       //   1- 1 - 0 (6) ATA Device ready to transfer data to host
#define ATA_INTR_WRITE  4       //   1- 0 - 0 (4) ATA Device ready to receive data from host
#define ATA_INTR_READY  3       //   0- 1 - 1 (3) ATA Device Processing Completed
#define ATA_INTR_ERROR  0       //   Return value in case of Device error
#define ATA_INTR_DMA    8       //   DMA Interrupt

#define ATA_IO_ERROR    9   
#define ATA_IO_SUCCESS  0


//
//  WaitForSingleObject Results
//
#define ATA_WFSO_OK         1
#define ATA_WFSO_TIMEOUT    2
#define ATA_WFSO_ERROR      4


//
// ATA error register bit masks.
//
#define ATA_ERROR_GENERAL          0x01
#define ATA_ERROR_ABORTED          0x04
#define ATA_ERROR_BAD_SECT_NUM     0x10
#define ATA_ERROR_UNCORRECTABLE    0x40
#define ATA_ERROR_BAD_BLOCK        0x80

//
// ATAPI error register bit masks.
//
#define ATAPI_ERR_ILLEGAL_LENGTH            0x01
#define ATAPI_ERR_END_OF_MEDIA              0x02
#define ATAPI_ERR_ABORTED_COMMAND           0x04
#define ATAPI_ERR_MEDIA_CHANGE_REQ          0x08
#define ATAPI_ERR_MEDIA_CHANGED             0x20
#define SENSE_KEYS                          0xF0    // Sense Key Descriptions page 183

// ATAPI Sense Key and Sense code definitions continued from above

#define ATAPI_SENSE_NOSENSE                 0x00
#define ATAPI_SENSE_RECOVERED_ERROR         0x10    
#define ATAPI_SENSE_NOT_READY               0x20    //
#define ATAPI_SENSE_MEDIUM_ERROR            0x30    //
#define ATAPI_SENSE_HARDWARE_ERROR          0x40    //
#define ATAPI_SENSE_ILLEGAL_REQUEST         0x50    //
#define ATAPI_SENSE_UNIT_ATTENTION          0x60    //
#define ATAPI_SENSE_DATA_PROTECT            0x70    //
#define ATAPI_SENSE_ABORTED_COMMAND         0xB0    //
#define ATAPI_SENSE_MISCOMPARE              0xE0    //

//
// ATA commands for the command register.
//
#define ATA_CMD_RECALIBRATE         0x10 // move drive heads to track 0
#define ATA_CMD_READ                0x20 // NO retries enabled
#define ATA_CMD_WRITE               0x30 // No retries enabled
#define ATA_CMD_MULTIPLE_READ       0xC4 // No retries enabled
#define ATA_CMD_MULTIPLE_WRITE      0xC5 // No retries enabled
#define ATA_CMD_SET_MULTIPLE        0xC6 // Set Multiple Mode 
#define ATA_CMD_SEEK                0x70
#define ATA_CMD_SET_DRIVE_PARMS     0x91 // set drive parameters
#define ATA_CMD_IDLE                0x97
#define ATA_CMD_IDENTIFY            0xEC // ATA identify drive parameters
#define ATA_CMD_ACKMEDIACHANGE      0xDB // Acknowledge media change
#define ATA_CMD_READ_DMA            0xC8 // DMA Read with retries
#define ATA_CMD_WRITE_DMA           0xCA // DMA Write with retries

//
// ATA commands for the features register.
//
#define ATA_SET_TRANSFER_MODE   0x03        // 

//
// The following values must be written into sector count register
// before setting transfer mode command into the features register.

#define ATA_PIO_DEFAULT_MODE    0       // PIO Default Mode
#define ATA_PIO_FCT_MODE        0x08    // PIO Flow Control Transfer Mode
#define ATA_DMA_ONE_WORD_MODE   0x10    // DMA Single Word Transfer Mode
#define ATA_DMA_MULTI_WORD_MODE 0x20    // DMA Multi-word Transfer Mode
#define ATA_DMA_PSEUDO_WORD_MOD 0x18    // Reserved  Mode



//
// ATAPI commands for the TASK command register.
//
#define ATAPI_CMD_COMMAND             0xA0 // move drive heads to track 0
#define ATAPI_CMD_IDENTIFY            0xA1 // identify drive parameters
#define ATAPI_CMD_SERVICE             0xA2 // Service
#define ATAPI_CMD_SOFT_RESET          0x08 // Soft Reset
#define ATAPI_CMD_SET_FEATURES        0xEF // Set Features

//
// ATAPI PACKET commands used by the TASK command 0xA0.
//

#define ATAPI_PACKET_CMD_TEST_READY     0x00 // Test unit ready
#define ATAPI_PACKET_CMD_REQUEST_SENSE  0x03 // Request additional status info
#define ATAPI_PACKET_CMD_INQUIRY        0x12 // Inquiry
#define ATAPI_PACKET_CMD_READ           0x28 // Read CD-DA format
#define ATAPI_PACKET_CMD_READ_12        0xA8 // 12 byte read command
#define ATAPI_PACKET_CMD_WRITE          0x2A // Read CD-DA format
#define ATAPI_PACKET_CMD_PAUSE_RESUME   0x4B // Pause/Resume
#define ATAPI_PACKET_CMD_PLAY           0x45 // Play
#define ATAPI_PACKET_CMD_PLAY_MSF       0x47 // Play MSF
#define ATAPI_PACKET_CMD_PLAY_CD        0xBC // Play CD
#define ATAPI_PACKET_CMD_SCAN_AUDIO     0xBA // Scan Audio
#define ATAPI_PACKET_CMD_READ_CAPACITY  0xBB // Read CD-ROM Capacity
#define ATAPI_PACKET_CMD_READ_CD        0xBE // Read CD-DA format
#define ATAPI_PACKET_CMD_READ_CD_MSF    0xB9 // Read CD-DA MSF format
#define ATAPI_PACKET_CMD_READ_HEADER    0x44 // Read Header
#define ATAPI_PACKET_CMD_READ_SUB_CHAN  0x42 // Read Sub Channel info
#define ATAPI_PACKET_CMD_READ_TOC       0x43 // Read Table of Contents
#define ATAPI_PACKET_CMD_SEEK           0x2B // Seek
#define ATAPI_PACKET_CMD_STOP_PLAY_SCAN 0x4E // Stop Play/Scan
#define ATAPI_PACKET_CMD_START_STOP     0x1B // Start/Stop Unit
#define ATAPI_PACKET_CMD_MODE_SENSE     0x5a // Mode Sense
#define ATAPI_PACKET_CMD_MODE_SELECT    0x55 // Mode Select
#define ATAPI_PACKET_CMD_SET_SPEED      0xBB // Set Speed

// DVD PACKET commands

    
//
// ATA status register bit masks.
//
#define ATA_STATUS_ERROR            0x01 // error bit in status register
#define ATA_STATUS_CORRECTED_ERROR  0x04 // corrected error in status register
#define ATA_STATUS_DATA_REQ         0x08 // data request bit in status register
#define ATA_STATUS_SEEK_DONE        0x10 // DSC - Drive Seek Complete
#define ATA_STATUS_WRITE_FAULT      0x20 // DWF - Drive Write Fault
#define ATA_STATUS_READY            0x40
#define ATA_STATUS_IDLE             0x50
#define ATA_STATUS_BUSY             0x80

//
// ATA drive select/head register bit masks.
//
#define ATA_HEAD_MUST_BE_ON         0xA0 // These 2 bits are always on
#define ATA_HEAD_DRIVE_1            (0x00 | ATA_HEAD_MUST_BE_ON)
#define ATA_HEAD_DRIVE_2            (0x10 | ATA_HEAD_MUST_BE_ON)
#define ATA_HEAD_LBA_MODE           (0x40 | ATA_HEAD_MUST_BE_ON)

//
// ATA device control register bit masks.
//
#define ATA_CTRL_ENABLE_INTR        0x00
#define ATA_CTRL_DISABLE_INTR       0x02
#define ATA_CTRL_RESET              0x04


//
// IDENTIFY capability bit definitions.
//

//#define IDENTIFY_CAPABILITIES_DMA_SUPPORTED 0x0100
//#define IDENTIFY_CAPABILITIES_LBA_SUPPORTED 0x0200

//
// IDENTIFY DMA timing cycle modes.
//

//
// IDE Cycle Timing
//
#define PIO_MODE0_CYCLE_TIME        600
#define PIO_MODE1_CYCLE_TIME        383
#define PIO_MODE2_CYCLE_TIME        240
#define PIO_MODE3_CYCLE_TIME        180
#define PIO_MODE4_CYCLE_TIME        120

#define SWDMA_MODE0_CYCLE_TIME      960
#define SWDMA_MODE1_CYCLE_TIME      480
#define SWDMA_MODE2_CYCLE_TIME      240

#define MWDMA_MODE0_CYCLE_TIME      480
#define MWDMA_MODE1_CYCLE_TIME      150
#define MWDMA_MODE2_CYCLE_TIME      120

#define UDMA_MODE0_CYCLE_TIME       120
#define UDMA_MODE1_CYCLE_TIME       80
#define UDMA_MODE2_CYCLE_TIME       60
#define UDMA_MODE3_CYCLE_TIME       45
#define UDMA_MODE4_CYCLE_TIME       30

//
// IDENTIFY DMA timing cycle modes.
//