fads.c

嵌入式ARM的一些源代码

	0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,

	/* refresh. (offset 30 in upm RAM) */
	0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
	0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,

	/* exception. (offset 3c in upm RAM) */
	0xeffffc06, 0x1ffffc07, 0xffffffff, 0xffffffff };

#elif defined(CONFIG_SDRAM_50MHZ)

/* ------------------------------------------------------------------------- */
/* sdram table stolen from the fads manual                                   */
/* for chip MB811171622A-100                                                 */

/* this table is for 32-50MHz operation */

#define _not_used_ 0xffffffff

#define SDRAM_MPTPRVALUE 0x0400

#define SDRAM_MBMRVALUE0 0x80802114   /* refresh at 32MHz */
#define SDRAM_MBMRVALUE1 0x80802118

#define SDRAM_OR4VALUE   0xffc00a00
#define SDRAM_BR4VALUE   0x000000c1   /* base address will be or:ed on */

#define SDRAM_MARVALUE   0x88

#define SDRAM_MCRVALUE0  0x80808105
#define SDRAM_MCRVALUE1  0x80808130

const uint sdram_table[] =
{
	/* single read. (offset 0 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	0x1ff77c47,

	/* MRS initialization (offset 5) */

	0x1ff77c34, 0xefeabc34, 0x1fb57c35,

	/* burst read. (offset 8 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* single write. (offset 18 in upm RAM) */
	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* burst write. (offset 20 in upm RAM) */
	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* refresh. (offset 30 in upm RAM) */
	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* exception. (offset 3c in upm RAM) */
	0x7ffffc07, _not_used_, _not_used_, _not_used_ };

/* ------------------------------------------------------------------------- */
#else
#error SDRAM not correctly configured
#endif

int _initsdram(uint base, uint noMbytes)
{
	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	if(noMbytes != 4)
	{
		return -1;
	}

	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));

	memctl->memc_mptpr = SDRAM_MPTPRVALUE;

	/* Configure the refresh (mostly).  This needs to be
	* based upon processor clock speed and optimized to provide
	* the highest level of performance.  For multiple banks,
	* this time has to be divided by the number of banks.
	* Although it is not clear anywhere, it appears the
	* refresh steps through the chip selects for this UPM
	* on each refresh cycle.
	* We have to be careful changing
	* UPM registers after we ask it to run these commands.
	*/

	memctl->memc_mbmr = SDRAM_MBMRVALUE0;
	memctl->memc_mar = SDRAM_MARVALUE;  /* MRS code */

	udelay(200);

	/* Now run the precharge/nop/mrs commands.
	*/

	memctl->memc_mcr = 0x80808111;   /* run pattern 0x11 */

	udelay(200);

	/* Run 8 refresh cycles */

	memctl->memc_mcr = SDRAM_MCRVALUE0;

	udelay(200);

	memctl->memc_mbmr = SDRAM_MBMRVALUE1;
	memctl->memc_mcr = SDRAM_MCRVALUE1;

	udelay(200);

	memctl->memc_mbmr = SDRAM_MBMRVALUE0;

	memctl->memc_or4 = SDRAM_OR4VALUE;
	memctl->memc_br4 = SDRAM_BR4VALUE | base;

	return 0;
}

/* ------------------------------------------------------------------------- */

void _sdramdisable(void)
{
	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_br4 = 0x00000000;

	/* maybe we should turn off upmb here or something */
}

/* ------------------------------------------------------------------------- */

int initsdram(uint base, uint *noMbytes)
{
	uint m = 4;

	*((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
								  /* _fads_sdraminit needs access to sdram */
	*noMbytes = m;

	if(!_initsdram(base, m))
	{

		return 0;
	}
	else
	{
		*((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */

		_sdramdisable();

		return -1;
	}
}

long int initdram (int board_type)
{
	uint base = (unsigned long)0x00400000;
	uint k, m, s;

	k = (*((uint *)BCSR2) >> 23) & 0x0f;

	m = 0;

	switch(k & 0x3)
	{
		/* "MCM36100 / MT8D132X" */
		case 0x00 :
			m = 4;
			break;

		/* "MCM36800 / MT16D832X" */
		case 0x01 :
			m = 32;
			break;
		/* "MCM36400 / MT8D432X" */
		case 0x02 :
			m = 16;
			break;
		/* "MCM36200 / MT16D832X ?" */
		case 0x03 :
			m = 8;
			break;

	}

	switch(k >> 2)
	{
		case 0x02 :
			k = 70;
			break;

		case 0x03 :
			k = 60;
			break;

		default :
			printf("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
			k = 70;
	}

#ifdef CONFIG_FADS
	/* the FADS is missing this bit, all rams treated as non-edo */
	s = 0;
#else
	s = (*((uint *)BCSR2) >> 27) & 0x01;
#endif

	if(!_draminit(base, m, s, k))
	{
		uint	sdramsz;

	    *((uint *)BCSR1) &= ~BCSR1_DRAM_EN;  /* enable dram */

#ifdef CONFIG_FADS
		if (!initsdram(0x00000000, &sdramsz)) {
				m += sdramsz;
				printf("(%u MB SDRAM) ", sdramsz);
		} else {
				_dramdisable();

				/********************************
				*DRAM ERROR, HALT PROCESSOR
				*********************************/
				while(1);

				return -1;
		}
#endif

		return (m << 20);
	}
	else
	{
		_dramdisable();

		/********************************
		*DRAM ERROR, HALT PROCESSOR
		*********************************/
		while(1);

		return -1;
	}
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
    /* TODO: XXX XXX XXX */
    printf ("test: 16 MB - ok\n");

    return (0);
}

#ifdef CONFIG_PCMCIA

#ifdef CFG_PCMCIA_MEM_ADDR
volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
#endif

int pcmcia_init(void)
{
	volatile pcmconf8xx_t	*pcmp;
	uint v, slota, slotb;

	/*
	** Enable the PCMCIA for a Flash card.
	*/
	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));

#if 0
	pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
	pcmp->pcmc_por0 = 0xc00ff05d;
#endif

	/* Set all slots to zero by default. */
	pcmp->pcmc_pgcra = 0;
	pcmp->pcmc_pgcrb = 0;
#ifdef PCMCIA_SLOT_A
	pcmp->pcmc_pgcra = 0x40;
#endif
#ifdef PCMCIA_SLOT_B
	pcmp->pcmc_pgcrb = 0x40;
#endif

	/* enable PCMCIA buffers */
	*((uint *)BCSR1) &= ~BCSR1_PCCEN;

	/* Check if any PCMCIA card is luged in. */

	slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;

	if (!(slota || slotb))
	{
		printf("No card present\n");
#ifdef PCMCIA_SLOT_A
		pcmp->pcmc_pgcra = 0;
#endif
#ifdef PCMCIA_SLOT_B
		pcmp->pcmc_pgcrb = 0;
#endif
		return -1;
	}
	    else
	printf("Unknown card (");

	v = 0;

	/* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
	**
	** Paolo - Yes, but i have to insert some 3.3V card in that slot on
	**	   my FADS... :-)
	*/

#if defined(CONFIG_MPC860)
	switch( (pcmp->pcmc_pipr >> 30) & 3 )
#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
	switch( (pcmp->pcmc_pipr >> 14) & 3 )
#endif
	{
		case 0x00 :
			printf("5V");
			v = 5;
			break;
		case 0x01 :
			printf("5V and 3V");
#ifdef CONFIG_FADS
			v = 3; // User lower voltage if supported!
#else
			v = 5;
#endif
			break;
		case 0x03 :
			printf("5V, 3V and x.xV");
#ifdef CONFIG_FADS
			v = 3; // User lower voltage if supported!
#else
			v = 5;
#endif
			break;
	}

	switch(v){
#ifdef CONFIG_FADS
	case 3:
	    printf("; using 3V");
	    /*
	    ** Enable 3 volt Vcc.
	    */
	    *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
	    *((uint *)BCSR1) |= BCSR1_PCCVCC0;
	    break;
#endif
	case 5:
	    printf("; using 5V");
#ifdef CONFIG_ADS
	    /*
	    ** Enable 5 volt Vcc.
	    */
	    *((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
#endif
#ifdef CONFIG_FADS
	    /*
	    ** Enable 5 volt Vcc.
	    */
	    *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
	    *((uint *)BCSR1) |= BCSR1_PCCVCC1;
#endif
	    break;

	default:
		*((uint *)BCSR1) |= BCSR1_PCCEN;  /* disable pcmcia */

		printf("; unknown voltage");
		return -1;
	}
	printf(")\n");
	/* disable pcmcia reset after a while */

	udelay(20);

#ifdef MPC860
	pcmp->pcmc_pgcra = 0;
#elif MPC823
	pcmp->pcmc_pgcrb = 0;
#endif

	/* If you using a real hd you should give a short
	* spin-up time. */
#ifdef CONFIG_DISK_SPINUP_TIME
	udelay(CONFIG_DISK_SPINUP_TIME);
#endif

	return 0;
}

#endif	/* CONFIG_PCMCIA */