fads.c

嵌入式ARM的一些源代码

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <ppcboot.h>
#include <config.h>
#include "mpc8xx.h"
#include "fads.h"

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

#if defined(CONFIG_DRAM_50MHZ)
/* 50MHz tables */
const uint dram_60ns[] =
{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
  0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff,
  0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
  0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
  0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
  0x3fffc847, 0xffffffff, 0xffffffff, 0xffffffff,
  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
  0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };

const uint dram_70ns[] =
{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
  0x00ffcc00, 0x37ffcc47, 0xffffffff, 0xffffffff,
  0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
  0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
  0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
  0x00ffec00, 0x3fffec47, 0xffffffff, 0xffffffff,
  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
  0x7fffcc06, 0xffffcc85, 0xffffcc05, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };

const uint edo_60ns[] =
{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
  0x00f3ec00, 0x37f7ec47, 0xffffffff, 0xffffffff,
  0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
  0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
  0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
  0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };

const uint edo_70ns[] =
{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
  0x00f3cc00, 0x37f7cc47, 0xffffffff, 0xffffffff,
  0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
  0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
  0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
  0x33f7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
  0x0cafcc00, 0x33bfcc47, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
  0x7fffcc04, 0xffffcc86, 0xffffcc05, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };

#elif defined(CONFIG_DRAM_25MHZ)

/* 25MHz tables */

const uint dram_60ns[] =
{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
  0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
  0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };

const uint dram_70ns[] =
{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
  0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
  0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };

const uint edo_60ns[] =
{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
  0x08f3cc00, 0x3ff7cc47, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
  0x08afcc48, 0x39bfcc47, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };

const uint edo_70ns[] =
{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
  0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
  0x3ff7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
  0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
  0x37bfcc47, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };


#else
#error dram not correct defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
#endif

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 *
 * Check for "L" type (no second DRAM bank),
 * otherwise "L" type is assumed as default.
 *
 * Return 1 for "L" type, 0 else.
 */

int checkboard (void)
{
	uint k;

	k = (*((uint *)BCSR3) >> 24) & 0x3f;

	switch(k)
	{
		case 0x03 :
		case 0x20 :
		case 0x21 :
		case 0x22 :
		case 0x23 :
		case 0x24 :
		case 0x3f :
			printf("FADS");
			break;

		default :
			printf("unknown board (0x%02x)\n", k);
			return -1;
	}

	printf(" with db ");

	switch(k)
	{
		case 0x03 :
			printf("MPC823");
			break;
		case 0x20 :
			printf("MPC801");
			break;
		case 0x21 :
			printf("MPC850");
			break;
		case 0x22 :
			printf("MPC821, MPC860 / MPC860SAR / MPC860T");
			break;
		case 0x23 :
			printf("MPC860SAR");
			break;
		case 0x24 :
			printf("MPC860T");
			break;
		case 0x3f :
			printf("MPC850SAR");
			break;
	}

	printf(" rev ");

	k = (((*((uint *)BCSR3) >> 23) & 1) << 3)
	| (((*((uint *)BCSR3) >> 19) & 1) << 2)
	| (((*((uint *)BCSR3) >> 16) & 3));

	switch(k)
	{
		case 0x01 :
			printf("ENG or PILOT\n");
			break;

		default:
			printf("unknown (0x%x)\n", k);
			return -1;
	}

	return 0;
}

/* ------------------------------------------------------------------------- */
int _draminit(uint base, uint noMbytes, uint edo, uint delay)
{
	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	/* init upm */

	switch(delay)
	{
		case 70:
		{
			if(edo)
			{
				upmconfig(UPMA, (uint *) edo_70ns, sizeof(edo_70ns)/sizeof(uint));
			}
			else
			{
				upmconfig(UPMA, (uint *) dram_70ns, sizeof(dram_70ns)/sizeof(uint));
			}

			break;
		}

		case 60:
		{
			if(edo)
			{
				upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
			}
			else
			{
				upmconfig(UPMA, (uint *) dram_60ns, sizeof(dram_60ns)/sizeof(uint));
			}

			break;
		}

		default :
			return -1;
	}

	memctl->memc_mptpr = 0x0400; /* divide by 16 */

	switch(noMbytes)
	{

		case 8:  /* 8 Mbyte uses both CS3 and CS2 */
		{
			memctl->memc_mamr = 0x13a01114;
			memctl->memc_or3 = 0xffc00800;
			memctl->memc_br3 = 0x00400081 + base;
			memctl->memc_or2 = 0xffc00800;
			break;
		}

		case 4: /* 4 Mbyte uses only CS2 */
		{
			memctl->memc_mamr = 0x13a01114;
			memctl->memc_or2 = 0xffc00800;
			break;
		}

		case 32: /* 32 Mbyte uses both CS3 and CS2 */
		{
			memctl->memc_mamr = 0x13b01114;
			memctl->memc_or3 = 0xff000800;
			memctl->memc_br3 = 0x01000081 + base;
			memctl->memc_or2 = 0xff000800;
			break;
		}

		case 16: /* 16 Mbyte uses only CS2 */
		{
			memctl->memc_mamr = 0x13b01114;
			memctl->memc_or2 = 0xff000800;
			break;
		}

		default:
		    return -1;
	}

	memctl->memc_br2 = 0x81 + base;     /* use upma */

	return 0;
}

/* ------------------------------------------------------------------------- */

void _dramdisable(void)
{
	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_br2 = 0x00000000;
	memctl->memc_br3 = 0x00000000;

	/* maybe we should turn off upma here or something */
}

#if defined(CONFIG_SDRAM_100MHZ)

/* ------------------------------------------------------------------------- */
/* sdram table by Dan Malek                                                  */

/* This has the stretched early timing so the 50 MHz
 * processor can make the 100 MHz timing.  This will
 * work at all processor speeds.
 */

#define SDRAM_MPTPRVALUE 0x0400

#define SDRAM_MBMRVALUE0 0xc3802114  /* (16-14) 50 MHz */
#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0

#define SDRAM_OR4VALUE   0xffc00a00
#define SDRAM_BR4VALUE   0x000000c1   /* base address will be or:ed on */

#define SDRAM_MARVALUE   0x88

#define SDRAM_MCRVALUE0  0x80808111   /* run pattern 0x11 */
#define SDRAM_MCRVALUE1  SDRAM_MCRVALUE0


const uint sdram_table[] =
{
	/* single read. (offset 0 in upm RAM) */
	0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
	0xefbbbc00, 0x1ff77c45, 0xffffffff, 0xffffffff,

	/* burst read. (offset 8 in upm RAM) */
	0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
	0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
	0x1ff77c45, 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
	0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff,

	/* single write. (offset 18 in upm RAM) */
	0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
	0x1ff77c45, 0xffffffff, 0xffffffff, 0xffffffff,

	/* burst write. (offset 20 in upm RAM) */
	0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,