cpu_init.c

嵌入式ARM的一些源代码

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <ppcboot.h>
#include <mpc8260.h>
#include <asm/cpm_8260.h>
#include <ioports.h>

static void
config_8260_ioports(volatile immap_t *immr)
{
    int portnum;

    for (portnum = 0; portnum < 4; portnum++) {
	uint pmsk = 0, ppar = 0, psor = 0, pdir = 0, podr = 0, pdat = 0;
	iop_conf_t *iopc = (iop_conf_t *)&iop_conf_tab[portnum][0];
	iop_conf_t *eiopc = iopc + 32;
	uint msk = 1;

	/* NOTE: index 0 refers to pin 31, index 31 refers to pin 0 */

	while (iopc < eiopc) {

	    if (iopc->conf) {
		pmsk |= msk;
		if (iopc->ppar) ppar |= msk;
		if (iopc->psor) psor |= msk;
		if (iopc->pdir) pdir |= msk;
		if (iopc->podr) podr |= msk;
		if (iopc->pdat) pdat |= msk;
	    }

	    msk <<= 1;
	    iopc++;
	}

	if (pmsk != 0) {
	    volatile ioport_t *iop = ioport_addr(immr, portnum);
	    uint tpmsk = ~pmsk;

	    /*
	     * the (somewhat confused) paragraph at the bottom of page 35-5
	     * warns that there might be "unknown behaviour" when programming
	     * PSORx and PDIRx, if PPARx = 1, so I decided this meant I had
	     * to disable the dedicated function first, and enable it last.
	     */
	    iop->ppar &= tpmsk;
	    iop->psor = (iop->psor & tpmsk) | psor;
	    iop->pdir = (iop->pdir & tpmsk) | pdir;
	    iop->podr = (iop->podr & tpmsk) | podr;
	    iop->pdat = (iop->pdat & tpmsk) | pdat;
	    iop->ppar |= ppar;
	}
    }
}

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void
cpu_init_f (volatile immap_t *immr)
{
    volatile	memctl8260_t *memctl = &immr->im_memctl;
    volatile	ulong count;
    init_data_t *idata = \
	(init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);

#if !defined(CONFIG_COGENT)	/* done in start.S for the cogent */
    /* SYPCR - contains watchdog control (11-9) */
    immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
#endif /* !CONFIG_COGENT */

#if defined(CONFIG_WATCHDOG)
    reset_8260_watchdog(immr);
#endif /* CONFIG_WATCHDOG */

    /* RSR - Reset Status Register - clear all status (5-4) */
    idata->reset_status = immr->im_clkrst.car_rsr;
    immr->im_clkrst.car_rsr = RSR_ALLBITS;

    /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
    immr->im_clkrst.car_rmr = CFG_RMR;

    /* BCR - Bus Configuration Register (4-25) */
    immr->im_siu_conf.sc_bcr = CFG_BCR;

    /* SIUMCR - contains debug pin configuration (4-31) */
    immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;

    config_8260_ioports(immr);

    /* initialize time counter status and control register (4-40) */
    immr->im_sit.sit_tmcntsc = CFG_TMCNTSC;

    /* initialize the PIT (4-42) */
    immr->im_sit.sit_piscr = CFG_PISCR;

#if !defined(CONFIG_COGENT)	/* done in start.S for the cogent */
    /* System clock control register (9-8) */
    immr->im_clkrst.car_sccr = CFG_SCCR;
#endif /* !CONFIG_COGENT */

    /*
     * Memory Controller:
     */

    /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
     * addresses - these have to be modified later when FLASH size
     * has been determined
     */

#if defined(CFG_OR0_REMAP)
    memctl->memc_or0 = CFG_OR0_REMAP;
#endif
#if defined(CFG_OR1_REMAP)
    memctl->memc_or1 = CFG_OR1_REMAP;
#endif

    /* now restrict to preliminary range */
    memctl->memc_br0 = CFG_BR0_PRELIM;
    memctl->memc_or0 = CFG_OR0_PRELIM;

#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
    memctl->memc_or1 = CFG_OR1_PRELIM;
    memctl->memc_br1 = CFG_BR1_PRELIM;
#endif

#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
    memctl->memc_or2 = CFG_OR2_PRELIM;
    memctl->memc_br2 = CFG_BR2_PRELIM;
#endif

#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
    memctl->memc_or3 = CFG_OR3_PRELIM;
    memctl->memc_br3 = CFG_BR3_PRELIM;
#endif

    /*
     * Reset CPM
     */
    immr->im_cpm.cp_cpcr = CPM_CR_RST;
    count = 0;
    do {				/* Spin until command processed		*/
	__asm__ __volatile__ ("eieio");
    } while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000);
}

/*
 * initialize higher level parts of CPU like time base and timers
 */
void
cpu_init_r  (bd_t *bd)
{
    volatile immap_t *immr = (immap_t *)bd->bi_immr_base;

    immr->im_cpm.cp_rccr = CFG_RCCR;
}

/*
 * print out the reason for the reset
 */
void
prt_8260_rsr(void)
{
    static struct {
	ulong mask;
	char *desc;
    } bits[] = {
	{ RSR_JTRS, "JTAG" },
	{ RSR_CSRS, "Check Stop" },
	{ RSR_SWRS, "Software Watchdog" },
	{ RSR_BMRS, "Bus Monitor" },
	{ RSR_ESRS, "External Soft" },
	{ RSR_EHRS, "External Hard" }
    };
    static int n = sizeof bits / sizeof bits[0];
    init_data_t *idata = \
	(init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
    ulong rsr = idata->reset_status;
    int i;

    printf("MPC8260 Reset Status\n");

    for (i = 0; i < n; i++)
	if (rsr & bits[i].mask)
	    printf(" - %s Reset\n", bits[i].desc);

    printf("\n");
}