📄 405gp_pci.c
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}
PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOLIMIT, ((IOLimit)>>8) & 0xF0, 1);
PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_IOLIMITUPPER16, ((IOLimit)>>16) & 0xFFFF, 2);
/* IOLIMIT is the starting address of a 4K block forwarded by the bridge. */
/* Round LowestIOAddr up to the next 4K boundary if IO space is enabled. */
if ((CommandReg_Val & 0x01) == 0x01)
LowestIOAddr = (IOLimit | 0xFFF) + 1;
MemLimit = LowestMemAddr1;
if ( LowestMemAddr1 > MemBase ) /* mem. space is used on secondary bus? */
{
CommandReg_Val |= 0x02; /* enable Memory Space */
MemLimit--; /* MemLimit is highest used address */
}
PCI_Write_CFG_Reg(BusDevFunc, PCIPCI_MEMLIMIT, ((MemLimit)>>16) & 0xFFF0, 2);
/* MEMLIMIT is the starting address of a 1M block forwarded by the bridge. */
/* Round LowestMemAddr up to the next 1M boundary if Memory space is enabled. */
if ( (CommandReg_Val & 0x02) == 0x02 )
LowestMemAddr1 = (MemLimit | 0xFFFFF) + 1;
/* Enable Bus Master on secondary bus */
CommandReg_Val |= 0x04;
PCI_Write_CFG_Reg(BusDevFunc, PCICMD, CommandReg_Val, 2);
}
/*-----------------------------------------------------------------------
| Subroutine: PCI_Find_Device
|
| Prototype: int PCI_Find_Device(hword VendorID, hword DeviceID);
|
| Description:
| Locate a PCI device by vendor and device number
|
| Inputs:
| VendorID Value of the device's Vendor ID field
| DeviceID Value of the device's Device ID field
|
| Return value:
| < 0 Device not found
| (int) PCI Bus+Device+Function number
+----------------------------------------------------------------------*/
int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID)
{
int Device;
int BusDevFunc;
int BusNum;
for (BusNum = MaxBusNum; BusNum >= 0; BusNum--)
for (Device = 0; Device < MAX_PCI_DEVICES; Device++)
{
BusDevFunc = (BusNum << 16) | (Device << 11);
if (PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID, 2) == VendorID
&& PCI_Read_CFG_Reg(BusDevFunc, PCIDEVICEID, 2) == DeviceID)
return (BusDevFunc);
}
return (-1);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCI)
void
do_pciinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
int bus_no = 0;
if (argc == 2)
{
bus_no = (int)simple_strtoul(argv[1], NULL, 10);
}
pciinfo(bus_no);
}
/*******************************************************************************
*
* pciinfo - print information about PCI devices
*
*/
void
pciinfo(int bus_no)
{
int device_no;
unsigned short vendor_id;
int BusDevFunc;
int device_no_start = 0;
printf ("Scanning function 0 of each PCI device on bus %d\n", bus_no);
if (bus_no == 0)
device_no_start = 1;
for (device_no=device_no_start; device_no < MAX_PCI_DEVICES; device_no++)
{
BusDevFunc = (bus_no << 16) | (device_no << 11);
vendor_id = PCI_Read_CFG_Reg(BusDevFunc, PCIVENDORID, 2);
if (vendor_id != 0xffff)
{
printf("\nFound PCI device %d:\n", device_no);
pciHeaderShow(BusDevFunc);
}
}
}
/*******************************************************************************
*
* pciHeaderShow - print a header of the specified PCI device
*
* This routine prints a header of the PCI device specified by BusDevFunc.
*
*/
void
pciHeaderShow(int BusDevFunc)
{
PCI_HEADER_DEVICE headerDevice;
PCI_HEADER_BRIDGE headerBridge;
PCI_HEADER_DEVICE * pD = &headerDevice;
PCI_HEADER_BRIDGE * pB = &headerBridge;
pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1);
if (pD->headerType & 0x01) /* PCI-to-PCI bridge */
{
pB->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2);
pB->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2);
pB->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2);
pB->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 2);
pB->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1);
pB->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1);
pB->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1);
pB->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1);
pB->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1);
pB->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1);
pB->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1);
pB->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1);
pB->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4);
pB->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4);
pB->priBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRIMARY_BUS, 1);
pB->secBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SECONDARY_BUS, 1);
pB->subBus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBORDINATE_BUS, 1);
pB->secLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_LATENCY, 1);
pB->ioBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE, 1);
pB->ioLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT, 1);
pB->secStatus = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SEC_STATUS, 2);
pB->memBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_BASE, 2);
pB->memLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MEM_LIMIT, 2);
pB->preBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE, 2);
pB->preLimit = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT, 2);
pB->preBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_BASE_U, 4);
pB->preLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PRE_MEM_LIMIT_U, 4);
pB->ioBaseUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_BASE_U, 2);
pB->ioLimitUpper = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_IO_LIMIT_U, 2);
pB->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_ROM_BASE, 4);
pB->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_LINE, 1);
pB->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRG_INT_PIN, 1);
pB->control = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BRIDGE_CONTROL, 2);
pciBheaderPrint(pB);
}
else /* PCI device */
{
pD->vendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_VENDOR_ID, 2);
pD->deviceId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEVICE_ID, 2);
pD->command = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_COMMAND, 2);
pD->status = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_STATUS, 1);
pD->revisionId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_REVISION, 1);
pD->progIf = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_PROGRAMMING_IF, 1);
pD->subClass = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUBCLASS, 1);
pD->classCode = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CLASS, 1);
pD->cacheLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CACHE_LINE_SIZE, 1);
pD->latency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_LATENCY_TIMER, 1);
pD->headerType = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_HEADER_TYPE, 1);
pD->bist = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BIST, 1);
pD->base0 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_0, 4);
pD->base1 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_1, 4);
pD->base2 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_2, 4);
pD->base3 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_3, 4);
pD->base4 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_4, 4);
pD->base5 = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_BASE_ADDRESS_5, 4);
pD->cis = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_CIS, 4);
pD->subVendorId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_VENDER_ID, 2);
pD->subSystemId = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_SUB_SYSTEM_ID, 2);
pD->romBase = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_EXPANSION_ROM, 4);
pD->intLine = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_LINE, 1);
pD->intPin = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_DEV_INT_PIN, 1);
pD->minGrant = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MIN_GRANT, 1);
pD->maxLatency = PCI_Read_CFG_Reg(BusDevFunc, PCI_CFG_MAX_LATENCY, 1);
pciDheaderPrint(pD);
}
}
/*******************************************************************************
*
* pciDheaderPrint - print a PCI device header
*
* This routine prints a PCI device header.
*
*/
void
pciDheaderPrint(PCI_HEADER_DEVICE * pD)
{
printf (" vendor ID = 0x%.4x\n", (ushort)pD->vendorId);
printf (" device ID = 0x%.4x\n", (ushort)pD->deviceId);
printf (" command register = 0x%.4x\n", (ushort)pD->command);
printf (" status register = 0x%.4x\n", (ushort)pD->status);
printf (" revision ID = 0x%.2x\n", (uchar)pD->revisionId);
printf (" class code = 0x%.2x\n", (uchar)pD->classCode);
printf (" sub class code = 0x%.2x\n", (uchar)pD->subClass);
printf (" programming interface = 0x%.2x\n", (uchar)pD->progIf);
printf (" cache line = 0x%.2x\n", (uchar)pD->cacheLine);
printf (" latency time = 0x%.2x\n", (uchar)pD->latency);
printf (" header type = 0x%.2x\n", (uchar)pD->headerType);
printf (" BIST = 0x%.2x\n", (uchar)pD->bist);
printf (" base address 0 = 0x%.8x\n", pD->base0);
printf (" base address 1 = 0x%.8x\n", pD->base1);
printf (" base address 2 = 0x%.8x\n", pD->base2);
printf (" base address 3 = 0x%.8x\n", pD->base3);
printf (" base address 4 = 0x%.8x\n", pD->base4);
printf (" base address 5 = 0x%.8x\n", pD->base5);
printf (" cardBus CIS pointer = 0x%.8x\n", pD->cis);
printf (" sub system vendor ID = 0x%.4x\n", (ushort)pD->subVendorId);
printf (" sub system ID = 0x%.4x\n", (ushort)pD->subSystemId);
printf (" expansion ROM base address = 0x%.8x\n", pD->romBase);
printf (" interrupt line = 0x%.2x\n", (uchar)pD->intLine);
printf (" interrupt pin = 0x%.2x\n", (uchar)pD->intPin);
printf (" min Grant = 0x%.2x\n", (uchar)pD->minGrant);
printf (" max Latency = 0x%.2x\n", (uchar)pD->maxLatency);
}
/*******************************************************************************
*
* pciBheaderPrint - print a PCI-to-PCI bridge header
*
* This routine prints a PCI-to-PCI bridge header.
*
*/
void
pciBheaderPrint(PCI_HEADER_BRIDGE * pB)
{
printf (" vendor ID = 0x%.4x\n", (ushort)pB->vendorId);
printf (" device ID = 0x%.4x\n", (ushort)pB->deviceId);
printf (" command register = 0x%.4x\n", (ushort)pB->command);
printf (" status register = 0x%.4x\n", (ushort)pB->status);
printf (" revision ID = 0x%.2x\n", (uchar)pB->revisionId);
printf (" class code = 0x%.2x\n", (uchar)pB->classCode);
printf (" sub class code = 0x%.2x\n", (uchar)pB->subClass);
printf (" programming interface = 0x%.2x\n", (uchar)pB->progIf);
printf (" cache line = 0x%.2x\n", (uchar)pB->cacheLine);
printf (" latency time = 0x%.2x\n", (uchar)pB->latency);
printf (" header type = 0x%.2x\n", (uchar)pB->headerType);
printf (" BIST = 0x%.2x\n", (uchar)pB->bist);
printf (" base address 0 = 0x%.8x\n", pB->base0);
printf (" base address 1 = 0x%.8x\n", pB->base1);
printf (" primary bus number = 0x%.2x\n", (uchar)pB->priBus);
printf (" secondary bus number = 0x%.2x\n", (uchar)pB->secBus);
printf (" subordinate bus number = 0x%.2x\n", (uchar)pB->subBus);
printf (" secondary latency timer = 0x%.2x\n", (uchar)pB->secLatency);
printf (" IO base = 0x%.2x\n", (uchar)pB->ioBase);
printf (" IO limit = 0x%.2x\n", (uchar)pB->ioLimit);
printf (" secondary status = 0x%.4x\n", (ushort)pB->secStatus);
printf (" memory base = 0x%.4x\n", (ushort)pB->memBase);
printf (" memory limit = 0x%.4x\n", (ushort)pB->memLimit);
printf (" prefetch memory base = 0x%.4x\n", (ushort)pB->preBase);
printf (" prefetch memory limit = 0x%.4x\n", (ushort)pB->preLimit);
printf (" prefetch memory base upper = 0x%.8x\n", pB->preBaseUpper);
printf (" prefetch memory limit upper = 0x%.8x\n", pB->preLimitUpper);
printf (" IO base upper 16 bits = 0x%.4x\n", (ushort)pB->ioBaseUpper);
printf (" IO limit upper 16 bits = 0x%.4x\n", (ushort)pB->ioLimitUpper);
printf (" expansion ROM base address = 0x%.8x\n", pB->romBase);
printf (" interrupt line = 0x%.2x\n", (uchar)pB->intLine);
printf (" interrupt pin = 0x%.2x\n", (uchar)pB->intPin);
printf (" bridge control = 0x%.4x\n", (ushort)pB->control);
}
#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
#endif /* CONFIG_PCI_PNP */
#endif /* CONFIG_PPC405GP */
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