config_cogent_mpc8260.h

嵌入式ARM的一些源代码

 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_ENV_ADDR	CFG_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
#define	CFG_FLASH_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
#define CFG_FLASH_ENV_BUF	(512*1024) /* see README - env sect real size */
#else
#define	CFG_FLASH_ENV_SIZE	0x4000	/* Total Size of Environment Sector	*/
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers			 2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
				HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2	0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn off Checkstop Reset Enable
 */
#define CFG_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn off Checkstop Reset Enable
 */
#define CFG_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
#define CFG_BCR		BCR_EBM

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
#define CFG_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 *
 * For some reason Cogent won't boot if bus monitor is enabled.
 * Don't know why.
 */
#if defined(CONFIG_COGENT)
# if defined(CONFIG_WATCHDOG)
#  define CFG_SYPCR	(SYPCR_SWTC|SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
# else
#  define CFG_SYPCR	0
# endif	/* CONFIG_WATCHDOG */
#else
# if defined(CONFIG_WATCHDOG)
#  define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
# else
#  define CFG_SYPCR	(SYPCR_BMT|SYPCR_PBME|SYPCR_LBME)
# endif	/* CONFIG_WATCHDOG */
#endif	/* CONFIG_COGENT */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CFG_SCCR	(SCCR_DFBRG01)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR	0

#if defined(CONFIG_CMA282)

/*
 * Init Memory Controller:
 *
 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
 * and CS2 for (optional) local bus RAM on the CPU module.
 *
 * We will also use CS1 to map the motherboard flash so that we can access
 * it with arbitrary port size. The reason for this is that there are two
 * address spaces for the Cogent motherboard flash: Execute and Read/Write.
 * Both access the same flash in different ways, but both have fixed
 * port size (Execute is 32 bits and Read/Write is 16 bits). We will only
 * access the Read/Write space with 16 bit accesses (via the flash driver),
 * but ppcboot uses various sized read accesses to "flash" (which is the
 * Execute space).
 *
 * Note the motherboard address space (256 Mbyte in size) is connected
 * to the 60x Bus and is located starting at address 0. The Hard Reset
 * Configuration Word should put the 60x Bus into External Bus Mode, since
 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
 *
 * (the *_SIZE vars must be a power of 2)
 */

#define CFG_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
#define CFG_CMA_CS0_SIZE	(1 << 20)
#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)		/* motherboard FLASH */
#define CFG_CMA_CS1_BASE	CMA_MB_FLASH_BASE
#define CFG_CMA_CS1_SIZE	CMA_MB_FLASH_SIZE
#endif
#if 0
#define CFG_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
#define CFG_CMA_CS2_SIZE	(16 << 20)
#endif

/*
 * CS0 maps the EPROM on the cpu module
 * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
 *
 * Note: We must have already transferred control to the final location
 * of the EPROM before these are used, because when BR0/OR0 are set, the
 * mirror of the eprom at any other addresses will disappear.
 */

/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
#define CFG_BR0_PRELIM	((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\
				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)

/*
 * We use CS1 to enable arbitrary port size access to the motherboard FLASH
 * (ppcboot needs this). Set it for 15 wait states, GPCM (60x BUS) mode.
 * The external bus master should terminate the transaction early (if I
 * understand this stuff correctly).
 */

#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/o, gpcm (60x bus) */
#define CFG_BR1_PRELIM	((CFG_CMA_CS1_BASE&BRx_BA_MSK)|BRx_PS_32|BRx_WP|BRx_V)
/* mask size CFG_CMA_CS1_SIZE, csneg 1/4 early, adr-to-cs 1/2, 15-wait states */
#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_CMA_CS1_SIZE)|\
				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_15_CLK)
#endif

/*
 * CS2 enables the Local Bus SDRAM on the CPU Module
 *
 * Will leave this unset for the moment, because a) my CPU module has no
 * SDRAM installed (it is optional); and b) it will require programming
 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
 * if you can't test it.
 */

#if 0
/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
#define CFG_BR0_PRELIM	((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
#endif

#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */