config_fads823.h

嵌入式ARM的一些源代码

 /*
  * A collection of structures, addresses, and values associated with
  * the Motorola 860T FADS board.  Copied from the MBX stuff.
  * Magnus Damm added defines for 8xxrom and extended bd_info.
  * Helmut Buchsbaum added bitvalues for BCSRx
  *
  * Copyright (c) 1998 Dan Malek ([e-mail])
  */

/*
 * 1999-nov-26: The FADS is using the following physical memorymap:
 *
 * ff020000 -> ff02ffff : pcmcia     io remapping
 * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by PPCBOOT
 * ff000000 -> ff00ffff : IMAP       internal in the cpu
 * e0000000 -> f3ffffff : pcmcia     memory remapping by m8xx_pcmcia
 * fe000000 -> fe1fffff : flash      connected to CS0, setup by PPCBOOT
 * 00000000 -> nnnnnnnn : sdram/dram setup by PPCBOOT
*/

#define CFG_PCMCIA_IO_ADDR	0xff020000
#define CFG_PCMCIA_IO_SIZE	0x10000
#define CFG_PCMCIA_MEM_ADDR	0xe0000000
#define CFG_PCMCIA_MEM_SIZE	0x10000
#define CFG_IMMR		0xFF000000
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x02800000
#define BCSR_ADDR		((uint) 0xff010000)
#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define	CONFIG_ETHADDR		08:00:22:50:70:63	// Ethernet address
#define CONFIG_ENV_OVERWRITE	1	// Overwrite the environment

#define CONFIG_VIDEO		1	// To enable video controller support
#define CONFIG_I2C		1	// To enable I2C support
#define CONFIG_PCMCIA		1	// To enable PCMCIA support

/* Video related */

#define CONFIG_VIDEO_LOGO			1	// Show the logo
#define CONFIG_VIDEO_ENCODER_AD7176		1	// Enable this encoder
#define CONFIG_VIDEO_ENCODER_AD7176_ADDR	0x54	// Default on fads
#define CONFIG_VIDEO_SIZE			(2*1024*1024)
#define CONFIG_VIDEO_ADDR (bd_ptr->bi_memsize - CONFIG_VIDEO_SIZE) // Frame buffer address

/* Wireless 56Khz 4PPM keyboard on SMCx */

//#define CONFIG_WL_4PPM_KEYBOARD		1
#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	// SMC to use (0 indexed)

/*
 * High Level Configuration Options
 * (easy to change)
 */
#include <mpc8xx_irq.h>

#define CONFIG_MPC823		1
#define CONFIG_MPC823FADS	1
#define CONFIG_FADS		1

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200

// Set the CPU speed to 50Mhz on the FADS

#if 0
#define MPC8XX_FACT	10			/* Multiply by 10		*/
#define MPC8XX_XIN	5000000			/* 5 MHz in	*/
#else
#define MPC8XX_FACT	10			/* Multiply by 10 */
#define MPC8XX_XIN	5000000			/* 5 MHz in */
#define CFG_PLPRCR_MF	(MPC8XX_FACT-1) << 20	/* From 0 to 4095 */
#endif
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))

#if 1
#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
#define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
#define CONFIG_BOOTARGS		""
#define CONFIG_BOOTCOMMAND							\
"bootp ;" 									\
"setenv bootargs console=tty0 console=ttyS0 " 					\
"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " 				\
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" 	\
"bootm"
#else
#define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
#endif

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_ALL

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory		*/
#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x01000000	/* 4 ... 16 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x00100000	/* default load address */

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR_SIZE		((uint)(64 * 1024))

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
#define	CFG_INIT_DATA_SIZE	64	/* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_INIT_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
 */
#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
#if 0
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
#endif
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_ENV_OFFSET 0x00040000	/* Offset of Environment Sector */
#define	CFG_FLASH_ENV_SIZE	0x40000	/* Total Size of Environment Sector	*/
/* the other CS:s are determined by looking at parameters in BCSRx */

/* values according to the manual */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control					11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SUMCR - SIU Module Configuration						11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control					11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer  *
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)