mpc8260.h

嵌入式ARM的一些源代码

#define HRCW_CDIS	0x20000000	/* Core Disable			*/
#define HRCW_EBM	0x10000000	/* External Bus Mode		*/
#define HRCW_BPS00	0x00000000	/* Boot Port Size		*/
#define HRCW_BPS01	0x04000000	/* - " -			*/
#define HRCW_BPS10	0x08000000	/* - " -			*/
#define HRCW_BPS11	0x0c000000	/* - " -			*/
#define HRCW_CIP	0x02000000	/* Core Initial Prefix		*/
#define HRCW_ISPS	0x01000000	/* Internal Space Port Size	*/
#define HRCW_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
#define HRCW_L2CPC01	0x00400000	/* - " -			*/
#define HRCW_L2CPC10	0x00800000	/* - " -			*/
#define HRCW_L2CPC11	0x00c00000	/* - " -			*/
#define HRCW_DPPC00	0x00000000	/* Data Parity Pin Configuration*/
#define HRCW_DPPC01	0x00100000	/* - " -			*/
#define HRCW_DPPC10	0x00200000	/* - " -			*/
#define HRCW_DPPC11	0x00300000	/* - " -			*/
#define HRCW_reserved1	0x00080000	/* reserved			*/
#define HRCW_ISB000	0x00000000	/* Initial Internal Space Base	*/
#define HRCW_ISB001	0x00010000	/* - " -			*/
#define HRCW_ISB010	0x00020000	/* - " -			*/
#define HRCW_ISB011	0x00030000	/* - " -			*/
#define HRCW_ISB100	0x00040000	/* - " -			*/
#define HRCW_ISB101	0x00050000	/* - " -			*/
#define HRCW_ISB110	0x00060000	/* - " -			*/
#define HRCW_ISB111	0x00070000	/* - " -			*/
#define HRCW_BMS	0x00008000	/* Boot Memory Space		*/
#define HRCW_BBD	0x00004000	/* Bus Busy Disable		*/
#define HRCW_MMR00	0x00000000	/* Mask Masters Requests	*/
#define HRCW_MMR01	0x00001000	/* - " -			*/
#define HRCW_MMR10	0x00002000	/* - " -			*/
#define HRCW_MMR11	0x00003000	/* - " -			*/
#define HRCW_LBPC00	0x00000000	/* Local Bus Pin Configuration	*/
#define HRCW_LBPC01	0x00000400	/* - " -			*/
#define HRCW_LBPC10	0x00000800	/* - " -			*/
#define HRCW_LBPC11	0x00000c00	/* - " -			*/
#define HRCW_APPC00	0x00000000	/* Address Parity Pin Configuration*/
#define HRCW_APPC01	0x00000100	/* - " -			*/
#define HRCW_APPC10	0x00000200	/* - " -			*/
#define HRCW_APPC11	0x00000300	/* - " -			*/
#define HRCW_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
#define HRCW_CS10PC01	0x00000040	/* - " -			*/
#define HRCW_CS10PC10	0x00000080	/* - " -			*/
#define HRCW_CS10PC11	0x000000c0	/* - " -			*/
#define HRCW_MODCK_H0000 0x00000000	/* High-order bits of MODCK Bus	*/
#define HRCW_MODCK_H0001 0x00000001	/* - " -			*/
#define HRCW_MODCK_H0010 0x00000002	/* - " -			*/
#define HRCW_MODCK_H0011 0x00000003	/* - " -			*/
#define HRCW_MODCK_H0100 0x00000004	/* - " -			*/
#define HRCW_MODCK_H0101 0x00000005	/* - " -			*/
#define HRCW_MODCK_H0110 0x00000006	/* - " -			*/
#define HRCW_MODCK_H0111 0x00000007	/* - " -			*/
#define HRCW_MODCK_H1000 0x00000008	/* - " -			*/
#define HRCW_MODCK_H1001 0x00000009	/* - " -			*/
#define HRCW_MODCK_H1010 0x0000000a	/* - " -			*/
#define HRCW_MODCK_H1011 0x0000000b	/* - " -			*/
#define HRCW_MODCK_H1100 0x0000000c	/* - " -			*/
#define HRCW_MODCK_H1101 0x0000000d	/* - " -			*/
#define HRCW_MODCK_H1110 0x0000000e	/* - " -			*/
#define HRCW_MODCK_H1111 0x0000000f	/* - " -			*/

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control Register					 9-8
 */
#define SCCR_CLPD	0x00000004	/* CPM Low Power Disable	*/
#define SCCR_DFBRG_MSK	0x00000003	/* Division factor of BRGCLK Mask */
#define SCCR_DFBRG_SHIFT 0

#define SCCR_DFBRG00	0x00000000	/* BRGCLK division by 4		*/
#define SCCR_DFBRG01	0x00000001	/* BRGCLK division by 16 (normal op.)*/
#define SCCR_DFBRG10	0x00000002	/* BRGCLK division by 64	*/
#define SCCR_DFBRG11	0x00000003	/* BRGCLK division by 128	*/

/*-----------------------------------------------------------------------
 * SCMR - System Clock Mode Register					 9-9
 */
#define SCMR_CORECNF_MSK 0x1f000000	/* Core Configuration Mask	*/
#define SCMR_CORECNF_SHIFT 24
#define SCMR_BUSDF_MSK	0x00f00000	/* 60x Bus Division Factor Mask	*/
#define SCMR_BUSDF_SHIFT 20
#define SCMR_CPMDF_MSK	0x000f0000	/* CPM Division Factor Mask	*/
#define SCMR_CPMDF_SHIFT 16
#define SCMR_PLLDF	0x00001000	/* PLL Pre-divider Value	*/
#define SCMR_PLLMF_MSK	0x00000fff	/* PLL Multiplication Factor Mask*/
#define SCMR_PLLMF_SHIFT 0


/*-----------------------------------------------------------------------
 * MxMR - Machine A/B/C Mode Registers					10-13
 */
#define MxMR_BSEL	0x80000000	/* Bus Select			*/
#define MxMR_RFEN	0x40000000	/* Refresh Enable		*/
#define MxMR_OP_MSK	0x30000000	/* Command Opcode Mask		*/
#define MxMR_AMx_MSK	0x07000000	/* Addess Multiplex Size Mask	*/
#define MxMR_DSx_MSK	0x00c00000	/* Disable Timer Period Mask	*/
#define MxMR_G0CLx_MSK	0x00380000	/* General Line 0 Control Mask	*/
#define MxMR_GPL_x4DIS	0x00040000	/* GPL_A4 Ouput Line Disable	*/
#define MxMR_RLFx_MSK	0x0003c000	/* Read Loop Field Mask		*/
#define MxMR_WLFx_MSK	0x00003c00	/* Write Loop Field Mask	*/
#define MxMR_TLFx_MSK	0x000003c0	/* Refresh Loop Field Mask	*/
#define MxMR_MAD_MSK	0x0000003f	/* Machine Address Mask		*/

#define MxMR_OP_NORM	0x00000000	/* Normal Operation		*/
#define MxMR_OP_WARR	0x10000000	/* Write to Array		*/
#define MxMR_OP_RARR	0x20000000	/* Read from Array		*/
#define MxMR_OP_RUNP	0x30000000	/* Run Pattern			*/

#define MxMR_AMx_TYPE_0 0x00000000	/* Addess Multiplexing Type 0	*/
#define MxMR_AMx_TYPE_1 0x01000000	/* Addess Multiplexing Type 1	*/
#define MxMR_AMx_TYPE_2 0x02000000	/* Addess Multiplexing Type 2	*/
#define MxMR_AMx_TYPE_3 0x03000000	/* Addess Multiplexing Type 3	*/
#define MxMR_AMx_TYPE_4 0x04000000	/* Addess Multiplexing Type 4	*/
#define MxMR_AMx_TYPE_5 0x05000000	/* Addess Multiplexing Type 5	*/

#define MxMR_DSx_1_CYCL 0x00000000	/* 1 cycle Disable Period	*/
#define MxMR_DSx_2_CYCL 0x00400000	/* 2 cycle Disable Period	*/
#define MxMR_DSx_3_CYCL 0x00800000	/* 3 cycle Disable Period	*/
#define MxMR_DSx_4_CYCL 0x00c00000	/* 4 cycle Disable Period	*/

#define MxMR_G0CLx_A12	0x00000000	/* General Line 0 : A12		*/
#define MxMR_G0CLx_A11	0x00080000	/* General Line 0 : A11		*/
#define MxMR_G0CLx_A10	0x00100000	/* General Line 0 : A10		*/
#define MxMR_G0CLx_A9	0x00180000	/* General Line 0 : A9		*/
#define MxMR_G0CLx_A8	0x00200000	/* General Line 0 : A8		*/
#define MxMR_G0CLx_A7	0x00280000	/* General Line 0 : A7		*/
#define MxMR_G0CLx_A6	0x00300000	/* General Line 0 : A6		*/
#define MxMR_G0CLx_A5	0x00380000	/* General Line 0 : A5		*/

#define MxMR_RLFx_1X	0x00004000	/* Read Loop is executed 1 time	*/
#define MxMR_RLFx_2X	0x00008000	/* Read Loop is executed 2 times*/
#define MxMR_RLFx_3X	0x0000c000	/* Read Loop is executed 3 times*/
#define MxMR_RLFx_4X	0x00010000	/* Read Loop is executed 4 times*/
#define MxMR_RLFx_5X	0x00014000	/* Read Loop is executed 5 times*/
#define MxMR_RLFx_6X	0x00018000	/* Read Loop is executed 6 times*/
#define MxMR_RLFx_7X	0x0001c000	/* Read Loop is executed 7 times*/
#define MxMR_RLFx_8X	0x00020000	/* Read Loop is executed 8 times*/
#define MxMR_RLFx_9X	0x00024000	/* Read Loop is executed 9 times*/
#define MxMR_RLFx_10X	0x00028000	/* Read Loop is executed 10 times*/
#define MxMR_RLFx_11X	0x0002c000	/* Read Loop is executed 11 times*/
#define MxMR_RLFx_12X	0x00030000	/* Read Loop is executed 12 times*/
#define MxMR_RLFx_13X	0x00034000	/* Read Loop is executed 13 times*/
#define MxMR_RLFx_14X	0x00038000	/* Read Loop is executed 14 times*/
#define MxMR_RLFx_15X	0x0003c000	/* Read Loop is executed 15 times*/
#define MxMR_RLFx_16X	0x00000000	/* Read Loop is executed 16 times*/

#define MxMR_WLFx_1X	0x00000400	/* Write Loop is executed 1 time*/
#define MxMR_WLFx_2X	0x00000800	/* Write Loop is executed 2 times*/
#define MxMR_WLFx_3X	0x00000c00	/* Write Loop is executed 3 times*/
#define MxMR_WLFx_4X	0x00001000	/* Write Loop is executed 4 times*/
#define MxMR_WLFx_5X	0x00001400	/* Write Loop is executed 5 times*/
#define MxMR_WLFx_6X	0x00001800	/* Write Loop is executed 6 times*/
#define MxMR_WLFx_7X	0x00001c00	/* Write Loop is executed 7 times*/
#define MxMR_WLFx_8X	0x00002000	/* Write Loop is executed 8 times*/
#define MxMR_WLFx_9X	0x00002400	/* Write Loop is executed 9 times*/
#define MxMR_WLFx_10X	0x00002800	/* Write Loop is executed 10 times*/
#define MxMR_WLFx_11X	0x00002c00	/* Write Loop is executed 11 times*/
#define MxMR_WLFx_12X	0x00003000	/* Write Loop is executed 12 times*/
#define MxMR_WLFx_13X	0x00003400	/* Write Loop is executed 13 times*/
#define MxMR_WLFx_14X	0x00003800	/* Write Loop is executed 14 times*/
#define MxMR_WLFx_15X	0x00003c00	/* Write Loop is executed 15 times*/
#define MxMR_WLFx_16X	0x00000000	/* Write Loop is executed 16 times*/

#define MxMR_TLFx_1X	0x00000040	/* Timer Loop is executed 1 time*/
#define MxMR_TLFx_2X	0x00000080	/* Timer Loop is executed 2 times*/
#define MxMR_TLFx_3X	0x000000c0	/* Timer Loop is executed 3 times*/
#define MxMR_TLFx_4X	0x00000100	/* Timer Loop is executed 4 times*/
#define MxMR_TLFx_5X	0x00000140	/* Timer Loop is executed 5 times*/
#define MxMR_TLFx_6X	0x00000180	/* Timer Loop is executed 6 times*/
#define MxMR_TLFx_7X	0x000001c0	/* Timer Loop is executed 7 times*/
#define MxMR_TLFx_8X	0x00000200	/* Timer Loop is executed 8 times*/
#define MxMR_TLFx_9X	0x00000240	/* Timer Loop is executed 9 times*/
#define MxMR_TLFx_10X	0x00000280	/* Timer Loop is executed 10 times*/
#define MxMR_TLFx_11X	0x000002c0	/* Timer Loop is executed 11 times*/
#define MxMR_TLFx_12X	0x00000300	/* Timer Loop is executed 12 times*/
#define MxMR_TLFx_13X	0x00000340	/* Timer Loop is executed 13 times*/
#define MxMR_TLFx_14X	0x00000380	/* Timer Loop is executed 14 times*/
#define MxMR_TLFx_15X	0x000003c0	/* Timer Loop is executed 15 times*/
#define MxMR_TLFx_16X	0x00000000	/* Timer Loop is executed 16 times*/


/*-----------------------------------------------------------------------
 * BRx - Memory Controller: Base Register				10-14
 */
#define BRx_BA_MSK	0xffff8000	/* Base Address Mask		*/
#define BRx_PS_MSK	0x00001800	/* Port Size Mask		*/
#define BRx_DECC_MSK	0x00000600	/* Data Error Correct+Check Mask*/
#define BRx_WP		0x00000100	/* Write Protect		*/
#define BRx_MS_MSK	0x000000e0	/* Machine Select Mask		*/
#define BRx_EMEMC	0x00000010	/* External MEMC Enable		*/
#define BRx_ATOM_MSK	0x0000000c	/* Atomic Operation Mask	*/
#define BRx_DR		0x00000002	/* Data Pipelining		*/
#define BRx_V		0x00000001	/* Bank Valid			*/

#define BRx_PS_64	0x00000000	/* 64 bit port size (60x bus only)*/
#define BRx_PS_8	0x00000800	/*  8 bit port size		*/
#define BRx_PS_16	0x00001000	/* 16 bit port size		*/
#define BRx_PS_32	0x00001800	/* 32 bit port size		*/

#define BRx_DECC_NONE	0x00000000	/* Data Errors Checking Disabled*/
#define BRx_DECC_NORMAL	0x00000200	/* Normal Parity Checking	*/
#define BRx_DECC_RMWPC	0x00000400	/* Read-Modify-Write Parity Checking*/
#define BRx_DECC_ECC	0x00000600	/* ECC Correction and Checking	*/

#define BRx_MS_GPCM_P	0x00000000	/* G.P.C.M. 60x Bus Machine Select*/
#define BRx_MS_GPCM_L	0x00000020	/* G.P.C.M. Local Bus Machine Select*/
#define BRx_MS_SDRAM_P	0x00000040	/* SDRAM 60x Bus Machine Select	*/
#define BRx_MS_SDRAM_L	0x00000060	/* SDRAM Local Bus Machine Select*/
#define BRx_MS_UPMA	0x00000080	/* U.P.M.A Machine Select	*/
#define BRx_MS_UPMB	0x000000a0	/* U.P.M.B Machine Select	*/
#define BRx_MS_UPMC	0x000000c0	/* U.P.M.C Machine Select	*/

#define BRx_ATOM_RAWA	0x00000004	/* Read-After-Write-Atomic	*/
#define BRx_ATOM_WARA	0x00000008	/* Write-After-Read-Atomic	*/

/*-----------------------------------------------------------------------
 * ORx - Memory Controller: Option Register - SDRAM Mode		10-16
 */
#define ORxS_SDAM_MSK	0xfff00000	/* SDRAM Address Mask Mask	*/
#define ORxS_LSDAM_MSK	0x000f8000	/* Lower SDRAM Address Mask Mask*/
#define ORxS_BPD_MSK	0x00006000	/* Banks Per Device Mask	*/
#define ORxS_ROWST_MSK	0x00001e00	/* Row Start Address Bit Mask	*/