mpc8xx.h

嵌入式ARM的一些源代码

#define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
#define MAMR_RLFA_4X	0x00000400	/* The Read Loop is executed 4 times	*/
#define MAMR_RLFA_5X	0x00000500	/* The Read Loop is executed 5 times	*/
#define MAMR_RLFA_6X	0x00000600	/* The Read Loop is executed 6 times	*/
#define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
#define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
#define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
#define MAMR_RLFA_10X	0x00000a00	/* The Read Loop is executed 10 times	*/
#define MAMR_RLFA_11X	0x00000b00	/* The Read Loop is executed 11 times	*/
#define MAMR_RLFA_12X	0x00000c00	/* The Read Loop is executed 12 times	*/
#define MAMR_RLFA_13X	0x00000d00	/* The Read Loop is executed 13 times	*/
#define MAMR_RLFA_14X	0x00000e00	/* The Read Loop is executed 14 times	*/
#define MAMR_RLFA_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
#define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
#define MAMR_WLFA_MSK	0x000000f0	/* Write Loop Field A mask		*/
#define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time	*/
#define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times	*/
#define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times	*/
#define MAMR_WLFA_4X	0x00000040	/* The Write Loop is executed 4 times	*/
#define MAMR_WLFA_5X	0x00000050	/* The Write Loop is executed 5 times	*/
#define MAMR_WLFA_6X	0x00000060	/* The Write Loop is executed 6 times	*/
#define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times	*/
#define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times	*/
#define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times	*/
#define MAMR_WLFA_10X	0x000000a0	/* The Write Loop is executed 10 times	*/
#define MAMR_WLFA_11X	0x000000b0	/* The Write Loop is executed 11 times	*/
#define MAMR_WLFA_12X	0x000000c0	/* The Write Loop is executed 12 times	*/
#define MAMR_WLFA_13X	0x000000d0	/* The Write Loop is executed 13 times	*/
#define MAMR_WLFA_14X	0x000000e0	/* The Write Loop is executed 14 times	*/
#define MAMR_WLFA_15X	0x000000f0	/* The Write Loop is executed 15 times	*/
#define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times	*/
#define MAMR_TLFA_MSK	0x0000000f	/* Timer Loop Field A mask		*/
#define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
#define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
#define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
#define MAMR_TLFA_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
#define MAMR_TLFA_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
#define MAMR_TLFA_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
#define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
#define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
#define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
#define MAMR_TLFA_10X	0x0000000a	/* The Timer Loop is executed 10 times	*/
#define MAMR_TLFA_11X	0x0000000b	/* The Timer Loop is executed 11 times	*/
#define MAMR_TLFA_12X	0x0000000c	/* The Timer Loop is executed 12 times	*/
#define MAMR_TLFA_13X	0x0000000d	/* The Timer Loop is executed 13 times	*/
#define MAMR_TLFA_14X	0x0000000e	/* The Timer Loop is executed 14 times	*/
#define MAMR_TLFA_15X	0x0000000f	/* The Timer Loop is executed 15 times	*/
#define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times	*/

/*-----------------------------------------------------------------------
 * Machine B Mode Register						16-13
 */
#define MAMR_PTB_MSK	0xff000000	/* Periodic Timer B period mask		*/
#define MAMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
#define MAMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
#define MAMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
#define MAMR_AMB_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
#define MAMR_AMB_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
#define MAMR_AMB_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
#define MAMR_AMB_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
#define MAMR_AMB_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
#define MAMR_AMB_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
#define MAMR_DSB_MSK	0x00060000	/* Disable Timer period mask		*/
#define MAMR_DSB_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
#define MAMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
#define MAMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
#define MAMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
#define MAMR_G0CLB_MSK	0x0000e000	/* General Line 0 Control B		*/
#define MAMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
#define MAMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
#define MAMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
#define MAMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
#define MAMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
#define MAMR_G0CLB_A7	0x0000a000	/* General Line 0 : A7			*/
#define MAMR_G0CLB_A6	0x0000b000	/* General Line 0 : A6			*/
#define MAMR_G0CLB_A5	0x0000e000	/* General Line 0 : A5			*/
#define MAMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
#define MAMR_RLFB_MSK	0x00000f00	/* Read Loop Field B mask		*/
#define MAMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
#define MAMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
#define MAMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
#define MAMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times	*/
#define MAMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times	*/
#define MAMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times	*/
#define MAMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
#define MAMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
#define MAMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
#define MAMR_RLFB_10X	0x00000a00	/* The Read Loop is executed 10 times	*/
#define MAMR_RLFB_11X	0x00000b00	/* The Read Loop is executed 11 times	*/
#define MAMR_RLFB_12X	0x00000c00	/* The Read Loop is executed 12 times	*/
#define MAMR_RLFB_13X	0x00000d00	/* The Read Loop is executed 13 times	*/
#define MAMR_RLFB_14X	0x00000e00	/* The Read Loop is executed 14 times	*/
#define MAMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
#define MAMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
#define MAMR_WLFB_MSK	0x000000f0	/* Write Loop Field B mask		*/
#define MAMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
#define MAMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
#define MAMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
#define MAMR_WLFB_4X	0x00000040	/* The Write Loop is executed 4 times	*/
#define MAMR_WLFB_5X	0x00000050	/* The Write Loop is executed 5 times	*/
#define MAMR_WLFB_6X	0x00000060	/* The Write Loop is executed 6 times	*/
#define MAMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
#define MAMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
#define MAMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
#define MAMR_WLFB_10X	0x000000a0	/* The Write Loop is executed 10 times	*/
#define MAMR_WLFB_11X	0x000000b0	/* The Write Loop is executed 11 times	*/
#define MAMR_WLFB_12X	0x000000c0	/* The Write Loop is executed 12 times	*/
#define MAMR_WLFB_13X	0x000000d0	/* The Write Loop is executed 13 times	*/
#define MAMR_WLFB_14X	0x000000e0	/* The Write Loop is executed 14 times	*/
#define MAMR_WLFB_15X	0x000000f0	/* The Write Loop is executed 15 times	*/
#define MAMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
#define MAMR_TLFB_MSK	0x0000000f	/* Timer Loop Field B mask		*/
#define MAMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
#define MAMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
#define MAMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
#define MAMR_TLFB_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
#define MAMR_TLFB_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
#define MAMR_TLFB_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
#define MAMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
#define MAMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
#define MAMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
#define MAMR_TLFB_10X	0x0000000a	/* The Timer Loop is executed 10 times	*/
#define MAMR_TLFB_11X	0x0000000b	/* The Timer Loop is executed 11 times	*/
#define MAMR_TLFB_12X	0x0000000c	/* The Timer Loop is executed 12 times	*/
#define MAMR_TLFB_13X	0x0000000d	/* The Timer Loop is executed 13 times	*/
#define MAMR_TLFB_14X	0x0000000e	/* The Timer Loop is executed 14 times	*/
#define MAMR_TLFB_15X	0x0000000f	/* The Timer Loop is executed 15 times	*/
#define MAMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/

/*-----------------------------------------------------------------------
 * Timer Global Configuration Register					18-8
 */
#define TGCR_CAS4	0x8000		/* Cascade Timer 3 and 4	*/
#define TGCR_FRZ4	0x4000		/* Freeze timer 4		*/
#define TGCR_STP4	0x2000		/* Stop timer   4		*/
#define TGCR_RST4	0x1000		/* Reset timer  4		*/
#define TGCR_GM2	0x0800		/* Gate Mode for Pin 2		*/
#define TGCR_FRZ3	0x0400		/* Freeze timer 3		*/
#define TGCR_STP3	0x0200		/* Stop timer   3		*/
#define TGCR_RST3	0x0100		/* Reset timer  3		*/
#define TGCR_CAS2	0x0080		/* Cascade Timer 1 and 2	*/
#define TGCR_FRZ2	0x0040		/* Freeze timer 2		*/
#define TGCR_STP2	0x0020		/* Stop timer   2		*/
#define TGCR_RST2	0x0010		/* Reset timer  2		*/
#define TGCR_GM1	0x0008		/* Gate Mode for Pin 1		*/
#define TGCR_FRZ1	0x0004		/* Freeze timer 1		*/
#define TGCR_STP1	0x0002		/* Stop timer   1		*/
#define TGCR_RST1	0x0001		/* Reset timer  1		*/


/*-----------------------------------------------------------------------
 * Timer Mode Register							18-9
 */
#define TMR_PS_MSK              0xff00  /* Prescaler Value 			*/
#define TMR_PS_SHIFT                 8  /* Prescaler position			*/
#define TMR_CE_MSK              0x00c0  /* Capture Edge and Enable Interrupt	*/
#define TMR_CE_INTR_DIS         0x0000  /* Disable Interrupt on capture event 	*/
#define TMR_CE_RISING           0x0040  /* Capture on Rising TINx edge only 	*/
#define TMR_CE_FALLING          0x0080  /* Capture on Falling TINx edge only 	*/
#define TMR_CE_ANY              0x00c0  /* Capture on any TINx edge 		*/
#define TMR_OM                  0x0020  /* Output Mode 				*/
#define TMR_ORI                 0x0010  /* Output Reference Interrupt Enable	*/
#define TMR_FRR                 0x0008  /* Free Run/Restart 			*/
#define TMR_ICLK_MSK            0x0006  /* Timer Input Clock Source mask 	*/
#define TMR_ICLK_IN_CAS         0x0000  /* Internally cascaded input 		*/
#define TMR_ICLK_IN_GEN         0x0002  /* Internal General system clock	*/
#define TMR_ICLK_IN_GEN_DIV16   0x0004  /* Internal General system clk div 16  	*/
#define TMR_ICLK_TIN_PIN        0x0006  /* TINx pin 				*/
#define TMR_GE                  0x0001  /* Gate Enable  			*/


/*-----------------------------------------------------------------------
 * PCMCIA Interface General Control Register				17-12
 */
#define	PCMCIA_GCRX_CXRESET	0x00000040
#define PCMCIA_GCRX_CXOE	0x00000080

#define PCMCIA_VS1(slot)	(0x80000000 >> (slot << 4))
#define PCMCIA_VS2(slot)	(0x40000000 >> (slot << 4))
#define PCMCIA_VS_MASK(slot)	(0xc0000000 >> (slot << 4))
#define PCMCIA_VS_SHIFT(slot)	(30 - (slot << 4))

#define PCMCIA_WP(slot)		(0x20000000 >> (slot << 4))
#define PCMCIA_CD2(slot)	(0x10000000 >> (slot << 4))
#define PCMCIA_CD1(slot)	(0x08000000 >> (slot << 4))
#define PCMCIA_BVD2(slot)	(0x04000000 >> (slot << 4))
#define PCMCIA_BVD1(slot)	(0x02000000 >> (slot << 4))
#define PCMCIA_RDY(slot)	(0x01000000 >> (slot << 4))
#define PCMCIA_RDY_L(slot)	(0x00800000 >> (slot << 4))
#define PCMCIA_RDY_H(slot)	(0x00400000 >> (slot << 4))
#define PCMCIA_RDY_R(slot)	(0x00200000 >> (slot << 4))
#define PCMCIA_RDY_F(slot)	(0x00100000 >> (slot << 4))
#define PCMCIA_MASK(slot)	(0xFFFF0000 >> (slot << 4))

/*-----------------------------------------------------------------------
 * PCMCIA Option Register Definitions
 *
 * Bank Sizes:
 */
#define PCMCIA_BSIZE_1		0x00000000	/* Bank size:   1 Bytes	*/
#define PCMCIA_BSIZE_2		0x08000000	/* Bank size:   2 Bytes	*/
#define PCMCIA_BSIZE_4		0x18000000	/* Bank size:   4 Bytes	*/
#define PCMCIA_BSIZE_8		0x10000000	/* Bank size:   8 Bytes	*/
#define PCMCIA_BSIZE_16		0x30000000	/* Bank size:  16 Bytes	*/
#define PCMCIA_BSIZE_32		0x38000000	/* Bank size:  32 Bytes	*/
#define PCMCIA_BSIZE_64		0x28000000	/* Bank size:  64 Bytes	*/
#define PCMCIA_BSIZE_128	0x20000000	/* Bank size: 128 Bytes	*/
#define PCMCIA_BSIZE_256	0x60000000	/* Bank size: 256 Bytes	*/
#define PCMCIA_BSIZE_512	0x68000000	/* Bank size: 512 Bytes	*/
#define PCMCIA_BSIZE_1K		0x78000000	/* Bank size:   1 kB	*/
#define PCMCIA_BSIZE_2K		0x70000000	/* Bank size:   2 kB	*/
#define PCMCIA_BSIZE_4K		0x50000000	/* Bank size:   4 kB	*/
#define PCMCIA_BSIZE_8K		0x58000000	/* Bank size:   8 kB	*/
#define PCMCIA_BSIZE_16K	0x48000000	/* Bank size:  16 kB	*/
#define PCMCIA_BSIZE_32K	0x40000000	/* Bank size:  32 kB	*/
#define PCMCIA_BSIZE_64K	0xC0000000	/* Bank size:  64 kB	*/
#define PCMCIA_BSIZE_128K	0xC8000000	/* Bank size: 128 kB	*/
#define PCMCIA_BSIZE_256K	0xD8000000	/* Bank size: 256 kB	*/
#define PCMCIA_BSIZE_512K	0xD0000000	/* Bank size: 512 kB	*/
#define PCMCIA_BSIZE_1M		0xF0000000	/* Bank size:   1 MB	*/
#define PCMCIA_BSIZE_2M		0xF8000000	/* Bank size:   2 MB	*/
#define PCMCIA_BSIZE_4M		0xE8000000	/* Bank size:   4 MB	*/
#define PCMCIA_BSIZE_8M		0xE0000000	/* Bank size:   8 MB	*/
#define PCMCIA_BSIZE_16M	0xA0000000	/* Bank size:  16 MB	*/
#define PCMCIA_BSIZE_32M	0xA8000000	/* Bank size:  32 MB	*/
#define PCMCIA_BSIZE_64M	0xB8000000	/* Bank size:  64 MB	*/

/* PCMCIA Timing */
#define PCMCIA_SHT(t)	((t & 0x0F)<<16)	/* Strobe Hold  Time 	*/
#define PCMCIA_SST(t)	((t & 0x0F)<<12)	/* Strobe Setup Time	*/
#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length	*/

/* PCMCIA Port Sizes */
#define PCMCIA_PPS_8		0x00000000	/*  8 bit port size	*/
#define PCMCIA_PPS_16		0x00000040	/* 16 bit port size	*/

/* PCMCIA Region Select */
#define PCMCIA_PRS_MEM		0x00000000	/* Common Memory Space	*/
#define PCMCIA_PRS_ATTR		0x00000010	/*     Attribute Space	*/
#define PCMCIA_PRS_IO		0x00000018	/*           I/O Space	*/
#define PCMCIA_PRS_DMA		0x00000020	/* DMA, normal transfer	*/
#define PCMCIA_PRS_DMA_LAST	0x00000028	/* DMA, last transactn	*/
#define PCMCIA_PRS_CEx		0x00000030	/* A[22:23] ==> CE1,CE2	*/

#define PCMCIA_PSLOT_A		0x00000000	/* Slot A		*/
#define PCMCIA_PSLOT_B		0x00000004	/* Slot B		*/
#define PCMCIA_WPROT		0x00000002	/* Write Protect	*/
#define PCMCIA_PV		0x00000001	/* Valid Bit		*/

#define UPMA	0x00000000
#define UPMB	0x00800000

#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
extern __inline__ void
reset_8xx_watchdog(volatile immap_t *immr)
{
	immr->im_siu_conf.sc_swsr = 0x556c;
	immr->im_siu_conf.sc_swsr = 0xaa39;
}
#endif	/* !__ASSEMBLY && CONFIG_WATCHDOG */

#endif	/* __MPCXX_H__ */