📄 mpc8xx.h
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mpc8xx.h
*
* MPC8xx specific definitions
*/
#ifndef __MPCXX_H__
#define __MPCXX_H__
/*-----------------------------------------------------------------------
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control Register 11-9
*/
#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */
#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration Register 11-6
*/
#define SIUMCR_EARB 0x80000000 /* External Arbitation */
#define SIUMCR_EARP111 0x70000000 /* Extern Arbi. Request prior. */
#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
#define SIUMCR_DBGC01 0x00200000 /* - " - */
#define SIUMCR_DBGC10 0x00400000 /* - " - */
#define SIUMCR_DBGC11 0x00600000 /* - " - */
#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
#define SIUMCR_DBPC01 0x00080000 /* - " - */
#define SIUMCR_DBPC10 0x00100000 /* - " - */
#define SIUMCR_DBPC11 0x00180000 /* - " - */
#define SIUMCR_FRC 0x00020000 /* FRZ pin Configuration */
#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
#define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */
#define SIUMCR_OPAR 0x00004000 /* Odd Parity */
#define SIUMCR_DPC 0x00002000 /* Data Parity pins Config. */
#define SIUMCR_MPRE 0x00001000 /* Multi CPU Reserva. Enable */
#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
#define SIUMCR_MLRC01 0x00000400 /* - " - */
#define SIUMCR_MLRC10 0x00000800 /* - " - */
#define SIUMCR_MLRC11 0x00000c00 /* - " - */
#define SIUMCR_AEME 0x00000200 /* Asynchro External Master */
#define SIUMCR_SEME 0x00000100 /* Synchro External Master */
#define SIUMCR_BSC 0x00000080 /* Byte Select Configuration */
#define SIUMCR_GB5E 0x00000040 /* GPL_B(5) Enable */
#define SIUMCR_B2DD 0x00000020 /* Bank 2 Double Drive */
#define SIUMCR_B3DD 0x00000010 /* Bank 3 Double Drive */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control Register 11-26
*/
#define TBSCR_TBIRQ7 0x8000 /* Time Base Interrupt Request 7 */
#define TBSCR_TBIRQ6 0x4000 /* Time Base Interrupt Request 6 */
#define TBSCR_TBIRQ5 0x2000 /* Time Base Interrupt Request 5 */
#define TBSCR_TBIRQ4 0x1000 /* Time Base Interrupt Request 4 */
#define TBSCR_TBIRQ3 0x0800 /* Time Base Interrupt Request 3 */
#define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */
#define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */
#define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */
#if 0 /* already in asm/8xx_immap.h */
#define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */
#define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */
#define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */
#define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */
#define TBSCR_TBF 0x0002 /* Time Base Freeze */
#define TBSCR_TBE 0x0001 /* Time Base Enable */
#endif
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control Register 11-31
*/
#undef PISCR_PIRQ /* TBD */
#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */
#if 0 /* already in asm/8xx_immap.h */
#define PISCR_PS 0x0080 /* Periodic interrupt Status */
#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
#endif
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*/
#define PLPRCR_MF_MSK 0xfff00000 /* Multiplication factor bits */
#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
#define PLPRCR_CSRC 0x00000400 /* Clock Source */
#define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */
#define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */
#define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */
#define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */
#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */
#define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */
#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
#define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */
#define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*/
#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
#define SCCR_COM10 0x40000000 /* reserved */
#define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */
#define SCCR_TBS 0x02000000 /* Time Base Source */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */
#define SCCR_CRQEN 0x00400000 /* CPM Request Enable */
#define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */
#define SCCR_EBDF00 0x00000000 /* CLKOUT is GCLK2 / 1 (normal op.) */
#define SCCR_EBDF01 0x00020000 /* CLKOUT is GCLK2 / 2 */
#define SCCR_EBDF10 0x00040000 /* reserved */
#define SCCR_EBDF11 0x00060000 /* reserved */
#define SCCR_DFSYNC00 0x00000000 /* SyncCLK division by 1 (normal op.) */
#define SCCR_DFSYNC01 0x00002000 /* SyncCLK division by 4 */
#define SCCR_DFSYNC10 0x00004000 /* SyncCLK division by 16 */
#define SCCR_DFSYNC11 0x00006000 /* SyncCLK division by 64 */
#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 1 (normal op.) */
#define SCCR_DFBRG01 0x00000800 /* BRGCLK division by 4 */
#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */
#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */
#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */
#define SCCR_DFNH111 0x000000E0 /* reserved */
#define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFLCD101 0x00000014 /* Division by 32 */
#define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */
#define SCCR_DFLCD111 0x0000001C /* reserved */
#define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFALCD01 0x00000001 /* Division by 3 */
#define SCCR_DFALCD10 0x00000002 /* Division by 5 */
#define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */
/*-----------------------------------------------------------------------
* BR - Memory Controler: Base Register 16-9
*/
#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
#define BR_AT_MSK 0x00007000 /* Address Type Mask */
#define BR_PS_MSK 0x00000c00 /* Port Size Mask */
#define BR_PARE 0x00000200 /* Parity Enable */
#define BR_WP 0x00000100 /* Write Protect */
#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
#define BR_V 0x00000001 /* Bank Valid */
#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_32 0x00000000 /* 32 bit port size */
/*-----------------------------------------------------------------------
* OR - Memory Controler: Option Register 16-11
*/
#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
/* Address Multiplex */
#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
#define OR_BI 0x00000100 /* Burst inhibit */
#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */
#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
#define OR_SETA 0x00000008 /* External Transfer Acknowledge */
#define OR_TRLX 0x00000004 /* Timing Relaxed */
#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
/*-----------------------------------------------------------------------
* MPTPR - Memory Periodic Timer Prescaler Register 16-17
*/
#define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */
#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */
#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */
#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */
#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */
#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
/*-----------------------------------------------------------------------
* Machine A Mode Register 16-13
*/
#define MAMR_PTA_MSK 0xff000000 /* Periodic Timer A period mask */
#define MAMR_PTA_SHIFT 0x00000018 /* Periodic Timer A period shift */
#define MAMR_PTAE 0x00800000 /* Periodic Timer A Enable */
#define MAMR_AMA_MSK 0x00700000 /* Addess Multiplexing size A */
#define MAMR_AMA_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
#define MAMR_AMA_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
#define MAMR_AMA_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
#define MAMR_AMA_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
#define MAMR_AMA_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
#define MAMR_AMA_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
#define MAMR_DSA_MSK 0x00060000 /* Disable Timer period mask */
#define MAMR_DSA_1_CYCL 0x00000000 /* 1 cycle Disable Period */
#define MAMR_DSA_2_CYCL 0x00020000 /* 2 cycle Disable Period */
#define MAMR_DSA_3_CYCL 0x00040000 /* 3 cycle Disable Period */
#define MAMR_DSA_4_CYCL 0x00060000 /* 4 cycle Disable Period */
#define MAMR_G0CLA_MSK 0x0000e000 /* General Line 0 Control A */
#define MAMR_G0CLA_A12 0x00000000 /* General Line 0 : A12 */
#define MAMR_G0CLA_A11 0x00002000 /* General Line 0 : A11 */
#define MAMR_G0CLA_A10 0x00004000 /* General Line 0 : A10 */
#define MAMR_G0CLA_A9 0x00006000 /* General Line 0 : A9 */
#define MAMR_G0CLA_A8 0x00008000 /* General Line 0 : A8 */
#define MAMR_G0CLA_A7 0x0000a000 /* General Line 0 : A7 */
#define MAMR_G0CLA_A6 0x0000b000 /* General Line 0 : A6 */
#define MAMR_G0CLA_A5 0x0000e000 /* General Line 0 : A5 */
#define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */
#define MAMR_RLFA_MSK 0x00000f00 /* Read Loop Field A mask */
#define MAMR_RLFA_1X 0x00000100 /* The Read Loop is executed 1 time */
#define MAMR_RLFA_2X 0x00000200 /* The Read Loop is executed 2 times */
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