evmdm642.c

dsp中关于I2C 的接收数据的操作

/*
 *  Copyright 2003 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 */

/*
 *  ======== evmdm642.c ========
 *  EVMDM642 board initializion implementation.
 */

#include <csl.h>
#include <csl_emifa.h>
#include <csl_i2c.h>
#include <csl_gpio.h>
#include <csl_cache.h>


#include "evmdm642_i2c.h"
#include "evmdm642_eeprom_i2c.h"
extern far void vectors();
/* I2C handle */
I2C_Handle I2C_hI2C;
my_Txinit()
{ 
    /* Configure I2C controller */
    I2C_config(I2C_hI2C, &myeepromXmtCfg);

    /* Take I2C out of reset */        
    I2C_outOfReset(I2C_hI2C);
}    


void intInit()
{
	//set irq
    IRQ_globalDisable();
    IRQ_setVecs(vectors);
    
	IRQ_map(IRQ_EVT_I2CINT0, 12);	 
	IRQ_clear     (IRQ_EVT_I2CINT0);	
	IRQ_enable    (IRQ_EVT_I2CINT0);  
	IRQ_globalEnable();  
		IRQ_nmiEnable();  
}

/* Initialize the board APIs */
void my_EVMDM642_init()
{
    volatile Uint32 test;
    
    EMIFA_Config emifaCfg0 = {
        EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK)    |
        EMIFA_FMKS(GBLCTL, EK2HZ, CLK)          |
        EMIFA_FMKS(GBLCTL, EK2EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS)    |
        EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE)     |
        EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ)        |
        EMIFA_FMKS(GBLCTL, EK1EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE)      |
        EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE),
        
        EMIFA_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFA_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, TA, DEFAULT)         |
        EMIFA_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, MTYPE, SDRAM64)      |
        EMIFA_FMKS(CECTL, RDHLD, DEFAULT),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(7))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC8)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(1)),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC32)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, SYNC32)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),
        
        EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS)       |
        EMIFA_FMKS(SDCTL, SDRSZ, 12ROW)        |
        EMIFA_FMKS(SDCTL, SDCSZ, 8COL)         |
        EMIFA_FMKS(SDCTL, RFEN, ENABLE)        |
        EMIFA_FMKS(SDCTL, INIT, YES)           |
        EMIFA_FMKS(SDCTL, TRCD, OF(1))         |
        EMIFA_FMKS(SDCTL, TRP, OF(1))          |
        EMIFA_FMKS(SDCTL, TRC, OF(5))          |
        EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
        
        EMIFA_FMKS(SDTIM, XRFR, OF(0))         |
        EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
        
        EMIFA_FMKS(SDEXT, WR2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, WR2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, WR2WR, OF(1))        |
        EMIFA_FMKS(SDEXT, R2WDQM, OF(3))       |
        EMIFA_FMKS(SDEXT, RD2WR, OF(2))        |
        EMIFA_FMKS(SDEXT, RD2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, RD2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, THZP, OF(2))         |
        EMIFA_FMKS(SDEXT, TWR, OF(2))          |
        EMIFA_FMKS(SDEXT, TRRD, OF(0))         |
        EMIFA_FMKS(SDEXT, TRAS, OF(6))         |
        EMIFA_FMKS(SDEXT, TCL, OF(1)),           
        
        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2)    |
        EMIFA_FMKS(CESEC, RENEN, READ)         |
        EMIFA_FMKS(CESEC, CEEXT, ACTIVE)       |
        EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE)      |
        EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
    };

    /* Initialize CSL */
    CSL_init();
    
    /* Unlock PERCFG through PCFGLOCK */
    *((unsigned long *)0x1b3f018) = 0x10c0010c;
    
    /* Enable VP0-VP2, I2C and McASP0 in PERCFG */
    *((unsigned long *)0x1b3f000) = 0x79;
    
    /* Read back PERCFG */
    test = *((unsigned long *)0x1b3f000);
    
    /* Wait at least 128 CPU cycles */
    waitusec(7);

    /* Initialize EMIFA */
    EMIFA_config(&emifaCfg0);

    /* Open I2C handle */
    I2C_hI2C = I2C_open(I2C_PORT0, I2C_OPEN_RESET);
	my_Txinit();
    /* Enable caching of SDRAM */
    CACHE_enableCaching(CACHE_EMIFA_CE00);
    CACHE_enableCaching(CACHE_EMIFA_CE01);
   
    intInit();
}


/* Spin in a delay loop for delay iterations */
void waitusec(Uint32 delay)
{
    volatile Uint32 i, n;
    
    n = 0;
    for (i = 0; i < delay*21; i++)
    {
        n = n + 1;
    }
}