pipemult_lc_new.map.eqn

来自「使用Quartus II 5.0开发指导手册」· EQN 代码 · 共 1,052 行 · 第 1/5 页

--K1_q_b[6] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[6]_PORT_A_data_in = F1_dataout_n[6];
K1_q_b[6]_PORT_A_data_in_reg = DFFE(K1_q_b[6]_PORT_A_data_in, K1_q_b[6]_clock_0, , , K1_q_b[6]_clock_enable_0);
K1_q_b[6]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[6]_PORT_A_address_reg = DFFE(K1_q_b[6]_PORT_A_address, K1_q_b[6]_clock_0, , , K1_q_b[6]_clock_enable_0);
K1_q_b[6]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
K1_q_b[6]_PORT_B_address_reg = DFFE(K1_q_b[6]_PORT_B_address, K1_q_b[6]_clock_1, , , );
K1_q_b[6]_PORT_A_write_enable = VCC;
K1_q_b[6]_PORT_A_write_enable_reg = DFFE(K1_q_b[6]_PORT_A_write_enable, K1_q_b[6]_clock_0, , , K1_q_b[6]_clock_enable_0);
K1_q_b[6]_PORT_B_read_enable = VCC;
K1_q_b[6]_PORT_B_read_enable_reg = DFFE(K1_q_b[6]_PORT_B_read_enable, K1_q_b[6]_clock_1, , , );
K1_q_b[6]_clock_0 = clk1;
K1_q_b[6]_clock_1 = clk1;
K1_q_b[6]_clock_enable_0 = wren;
K1_q_b[6]_PORT_B_data_out = MEMORY(K1_q_b[6]_PORT_A_data_in_reg, , K1_q_b[6]_PORT_A_address_reg, K1_q_b[6]_PORT_B_address_reg, K1_q_b[6]_PORT_A_write_enable_reg, K1_q_b[6]_PORT_B_read_enable_reg, , , K1_q_b[6]_clock_0, K1_q_b[6]_clock_1, K1_q_b[6]_clock_enable_0, , , );
K1_q_b[6] = K1_q_b[6]_PORT_B_data_out[0];


--K1_q_b[5] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[5]_PORT_A_data_in = F1_dataout_n[5];
K1_q_b[5]_PORT_A_data_in_reg = DFFE(K1_q_b[5]_PORT_A_data_in, K1_q_b[5]_clock_0, , , K1_q_b[5]_clock_enable_0);
K1_q_b[5]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[5]_PORT_A_address_reg = DFFE(K1_q_b[5]_PORT_A_address, K1_q_b[5]_clock_0, , , K1_q_b[5]_clock_enable_0);
K1_q_b[5]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
K1_q_b[5]_PORT_B_address_reg = DFFE(K1_q_b[5]_PORT_B_address, K1_q_b[5]_clock_1, , , );
K1_q_b[5]_PORT_A_write_enable = VCC;
K1_q_b[5]_PORT_A_write_enable_reg = DFFE(K1_q_b[5]_PORT_A_write_enable, K1_q_b[5]_clock_0, , , K1_q_b[5]_clock_enable_0);
K1_q_b[5]_PORT_B_read_enable = VCC;
K1_q_b[5]_PORT_B_read_enable_reg = DFFE(K1_q_b[5]_PORT_B_read_enable, K1_q_b[5]_clock_1, , , );
K1_q_b[5]_clock_0 = clk1;
K1_q_b[5]_clock_1 = clk1;
K1_q_b[5]_clock_enable_0 = wren;
K1_q_b[5]_PORT_B_data_out = MEMORY(K1_q_b[5]_PORT_A_data_in_reg, , K1_q_b[5]_PORT_A_address_reg, K1_q_b[5]_PORT_B_address_reg, K1_q_b[5]_PORT_A_write_enable_reg, K1_q_b[5]_PORT_B_read_enable_reg, , , K1_q_b[5]_clock_0, K1_q_b[5]_clock_1, K1_q_b[5]_clock_enable_0, , , );
K1_q_b[5] = K1_q_b[5]_PORT_B_data_out[0];


--K1_q_b[4] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[4]_PORT_A_data_in = F1_dataout_n[4];
K1_q_b[4]_PORT_A_data_in_reg = DFFE(K1_q_b[4]_PORT_A_data_in, K1_q_b[4]_clock_0, , , K1_q_b[4]_clock_enable_0);
K1_q_b[4]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[4]_PORT_A_address_reg = DFFE(K1_q_b[4]_PORT_A_address, K1_q_b[4]_clock_0, , , K1_q_b[4]_clock_enable_0);
K1_q_b[4]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
K1_q_b[4]_PORT_B_address_reg = DFFE(K1_q_b[4]_PORT_B_address, K1_q_b[4]_clock_1, , , );
K1_q_b[4]_PORT_A_write_enable = VCC;
K1_q_b[4]_PORT_A_write_enable_reg = DFFE(K1_q_b[4]_PORT_A_write_enable, K1_q_b[4]_clock_0, , , K1_q_b[4]_clock_enable_0);
K1_q_b[4]_PORT_B_read_enable = VCC;
K1_q_b[4]_PORT_B_read_enable_reg = DFFE(K1_q_b[4]_PORT_B_read_enable, K1_q_b[4]_clock_1, , , );
K1_q_b[4]_clock_0 = clk1;
K1_q_b[4]_clock_1 = clk1;
K1_q_b[4]_clock_enable_0 = wren;
K1_q_b[4]_PORT_B_data_out = MEMORY(K1_q_b[4]_PORT_A_data_in_reg, , K1_q_b[4]_PORT_A_address_reg, K1_q_b[4]_PORT_B_address_reg, K1_q_b[4]_PORT_A_write_enable_reg, K1_q_b[4]_PORT_B_read_enable_reg, , , K1_q_b[4]_clock_0, K1_q_b[4]_clock_1, K1_q_b[4]_clock_enable_0, , , );
K1_q_b[4] = K1_q_b[4]_PORT_B_data_out[0];


--K1_q_b[3] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[3]_PORT_A_data_in = F1_dataout_n[3];
K1_q_b[3]_PORT_A_data_in_reg = DFFE(K1_q_b[3]_PORT_A_data_in, K1_q_b[3]_clock_0, , , K1_q_b[3]_clock_enable_0);
K1_q_b[3]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[3]_PORT_A_address_reg = DFFE(K1_q_b[3]_PORT_A_address, K1_q_b[3]_clock_0, , , K1_q_b[3]_clock_enable_0);
K1_q_b[3]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
K1_q_b[3]_PORT_B_address_reg = DFFE(K1_q_b[3]_PORT_B_address, K1_q_b[3]_clock_1, , , );
K1_q_b[3]_PORT_A_write_enable = VCC;
K1_q_b[3]_PORT_A_write_enable_reg = DFFE(K1_q_b[3]_PORT_A_write_enable, K1_q_b[3]_clock_0, , , K1_q_b[3]_clock_enable_0);
K1_q_b[3]_PORT_B_read_enable = VCC;
K1_q_b[3]_PORT_B_read_enable_reg = DFFE(K1_q_b[3]_PORT_B_read_enable, K1_q_b[3]_clock_1, , , );
K1_q_b[3]_clock_0 = clk1;
K1_q_b[3]_clock_1 = clk1;
K1_q_b[3]_clock_enable_0 = wren;
K1_q_b[3]_PORT_B_data_out = MEMORY(K1_q_b[3]_PORT_A_data_in_reg, , K1_q_b[3]_PORT_A_address_reg, K1_q_b[3]_PORT_B_address_reg, K1_q_b[3]_PORT_A_write_enable_reg, K1_q_b[3]_PORT_B_read_enable_reg, , , K1_q_b[3]_clock_0, K1_q_b[3]_clock_1, K1_q_b[3]_clock_enable_0, , , );
K1_q_b[3] = K1_q_b[3]_PORT_B_data_out[0];


--K1_q_b[2] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[2]_PORT_A_data_in = F1_dataout_n[2];
K1_q_b[2]_PORT_A_data_in_reg = DFFE(K1_q_b[2]_PORT_A_data_in, K1_q_b[2]_clock_0, , , K1_q_b[2]_clock_enable_0);
K1_q_b[2]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[2]_PORT_A_address_reg = DFFE(K1_q_b[2]_PORT_A_address, K1_q_b[2]_clock_0, , , K1_q_b[2]_clock_enable_0);
K1_q_b[2]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
K1_q_b[2]_PORT_B_address_reg = DFFE(K1_q_b[2]_PORT_B_address, K1_q_b[2]_clock_1, , , );
K1_q_b[2]_PORT_A_write_enable = VCC;
K1_q_b[2]_PORT_A_write_enable_reg = DFFE(K1_q_b[2]_PORT_A_write_enable, K1_q_b[2]_clock_0, , , K1_q_b[2]_clock_enable_0);
K1_q_b[2]_PORT_B_read_enable = VCC;
K1_q_b[2]_PORT_B_read_enable_reg = DFFE(K1_q_b[2]_PORT_B_read_enable, K1_q_b[2]_clock_1, , , );
K1_q_b[2]_clock_0 = clk1;
K1_q_b[2]_clock_1 = clk1;
K1_q_b[2]_clock_enable_0 = wren;
K1_q_b[2]_PORT_B_data_out = MEMORY(K1_q_b[2]_PORT_A_data_in_reg, , K1_q_b[2]_PORT_A_address_reg, K1_q_b[2]_PORT_B_address_reg, K1_q_b[2]_PORT_A_write_enable_reg, K1_q_b[2]_PORT_B_read_enable_reg, , , K1_q_b[2]_clock_0, K1_q_b[2]_clock_1, K1_q_b[2]_clock_enable_0, , , );
K1_q_b[2] = K1_q_b[2]_PORT_B_data_out[0];


--K1_q_b[1] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[1]_PORT_A_data_in = F1_dataout_n[1];
K1_q_b[1]_PORT_A_data_in_reg = DFFE(K1_q_b[1]_PORT_A_data_in, K1_q_b[1]_clock_0, , , K1_q_b[1]_clock_enable_0);
K1_q_b[1]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[1]_PORT_A_address_reg = DFFE(K1_q_b[1]_PORT_A_address, K1_q_b[1]_clock_0, , , K1_q_b[1]_clock_enable_0);
K1_q_b[1]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
K1_q_b[1]_PORT_B_address_reg = DFFE(K1_q_b[1]_PORT_B_address, K1_q_b[1]_clock_1, , , );
K1_q_b[1]_PORT_A_write_enable = VCC;
K1_q_b[1]_PORT_A_write_enable_reg = DFFE(K1_q_b[1]_PORT_A_write_enable, K1_q_b[1]_clock_0, , , K1_q_b[1]_clock_enable_0);
K1_q_b[1]_PORT_B_read_enable = VCC;
K1_q_b[1]_PORT_B_read_enable_reg = DFFE(K1_q_b[1]_PORT_B_read_enable, K1_q_b[1]_clock_1, , , );
K1_q_b[1]_clock_0 = clk1;
K1_q_b[1]_clock_1 = clk1;
K1_q_b[1]_clock_enable_0 = wren;
K1_q_b[1]_PORT_B_data_out = MEMORY(K1_q_b[1]_PORT_A_data_in_reg, , K1_q_b[1]_PORT_A_address_reg, K1_q_b[1]_PORT_B_address_reg, K1_q_b[1]_PORT_A_write_enable_reg, K1_q_b[1]_PORT_B_read_enable_reg, , , K1_q_b[1]_clock_0, K1_q_b[1]_clock_1, K1_q_b[1]_clock_enable_0, , , );
K1_q_b[1] = K1_q_b[1]_PORT_B_data_out[0];


--K1_q_b[0] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[0]_PORT_A_data_in = F1_dataout_n[0];
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L3Q, C1L4Q, C1L5Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = clk1;
K1_q_b[0]_clock_1 = clk1;
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[0] = K1_q_b[0]_PORT_B_data_out[0];


--F1_dataout_n[15] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[15]
F1_dataout_n[15] = DFFEAS(H1L45, clk1,  ,  ,  ,  ,  ,  ,  );


--C1L1Q is ram:inst1|ram_block~0
C1L1Q = DFFEAS(rdaddress[0], clk1,  ,  ,  ,  ,  ,  ,  );


--C1L2Q is ram:inst1|ram_block~1
C1L2Q = DFFEAS(rdaddress[1], clk1,  ,  ,  ,  ,  ,  ,  );


--C1L3Q is ram:inst1|ram_block~2
C1L3Q = DFFEAS(rdaddress[2], clk1,  ,  ,  ,  ,  ,  ,  );


--C1L4Q is ram:inst1|ram_block~3
C1L4Q = DFFEAS(rdaddress[3], clk1,  ,  ,  ,  ,  ,  ,  );


--C1L5Q is ram:inst1|ram_block~4
C1L5Q = DFFEAS(rdaddress[4], clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[14] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[14]
F1_dataout_n[14] = DFFEAS(H1L05, clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[13] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[13]
F1_dataout_n[13] = DFFEAS(H1L64, clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[12] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[12]
F1_dataout_n[12] = DFFEAS(H1L24, clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[11] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[11]
F1_dataout_n[11] = DFFEAS(H1L83, clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[10] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[10]
F1_dataout_n[10] = DFFEAS(H1L43, clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[9] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[9]
F1_dataout_n[9] = DFFEAS(H1L03, clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[8] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[8]
F1_dataout_n[8] = DFFEAS(H1L62, clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[7] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[7]
F1_dataout_n[7] = DFFEAS(H1L22, clk1,  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[6] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[6]