mult_edq.tdf

使用Quartus II 5.0开发指导手册

--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" DSP_BLOCK_BALANCING="Auto" LPM_PIPELINE=2 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=8 LPM_WIDTHB=8 LPM_WIDTHP=16 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_mult 2005:02:22:16:29:30:SJ cbx_mgl 2005:04:13:17:26:48:SJ cbx_padd 2005:04:14:12:08:54:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION stratixii_mac_mult (aclr[3..0], clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], ena[3..0], mode, round, saturate, scanina[dataa_width-1..0], scaninb[datab_width-1..0], signa, signb, sourcea, sourceb, zeroacc)
WITH ( 	bypass_multiplier,	dataa_clear,	dataa_clock,	dataa_width,	datab_clear,	datab_clock,	datab_width,	mode_clear,	mode_clock,	output_clear,	output_clock,	round_clear,	round_clock,	saturate_clear,	saturate_clock,	signa_clear,	signa_clock,	signa_internally_grounded,	signb_clear,	signb_clock,	signb_internally_grounded,	zeroacc_clear,	zeroacc_clock) 
RETURNS ( dataout[dataa_width+datab_width-1..0], scanouta[dataa_width-1..0], scanoutb[datab_width-1..0]);
PARAMETERS
(
	dataa_width = 1,
	datab_width = 1,
	datac_width = 1,
	datad_width = 1,
	dataout_width = 144
);
FUNCTION stratixii_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], datac[datac_width-1..0], datad[datad_width-1..0], ena[3..0], mode0, mode1, multabsaturate, multcdsaturate, round0, round1, saturate, saturate1, signa, signb, zeroacc, zeroacc1)
WITH ( 	addnsub0_clear,	addnsub0_clock,	addnsub0_pipeline_clear,	addnsub0_pipeline_clock,	addnsub1_clear,	addnsub1_clock,	addnsub1_pipeline_clear,	addnsub1_pipeline_clock,	dataa_forced_to_zero,	dataa_width,	datab_width,	datac_forced_to_zero,	datac_width,	datad_width,	dataout_width,	mode0_clear,	mode0_clock,	mode0_pipeline_clear,	mode0_pipeline_clock,	mode1_clear,	mode1_clock,	mode1_pipeline_clear,	mode1_pipeline_clock,	multabsaturate_clear,	multabsaturate_clock,	multabsaturate_pipeline_clear,	multabsaturate_pipeline_clock,	multcdsaturate_clear,	multcdsaturate_clock,	multcdsaturate_pipeline_clear,	multcdsaturate_pipeline_clock,	operation_mode,	output1_clear,	output1_clock,	output2_clear,	output2_clock,	output3_clear,	output3_clock,	output4_clear,	output4_clock,	output5_clear,	output5_clock,	output6_clear,	output6_clock,	output7_clear,	output7_clock,	output_clear,	output_clock,	round0_clear,	round0_clock,	round0_pipeline_clear,	round0_pipeline_clock,	round1_clear,	round1_clock,	round1_pipeline_clear,	round1_pipeline_clock,	saturate1_clear,	saturate1_clock,	saturate1_pipeline_clear,	saturate1_pipeline_clock,	saturate_clear,	saturate_clock,	saturate_pipeline_clear,	saturate_pipeline_clock,	signa_clear,	signa_clock,	signa_pipeline_clear,	signa_pipeline_clock,	signb_clear,	signb_clock,	signb_pipeline_clear,	signb_pipeline_clock,	zeroacc1_clear,	zeroacc1_clock,	zeroacc1_pipeline_clear,	zeroacc1_pipeline_clock,	zeroacc_clear,	zeroacc_clock,	zeroacc_pipeline_clear,	zeroacc_pipeline_clock) 
RETURNS ( accoverflow, dataout[dataout_width-1..0]);

--synthesis_resources = dsp_9bit 1 
SUBDESIGN mult_edq
( 
	clock	:	input;
	dataa[7..0]	:	input;
	datab[7..0]	:	input;
	result[15..0]	:	output;
) 
VARIABLE 
	mac_mult2 : stratixii_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 8,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 8,
			output_clear = "0",
			output_clock = "0"
		);
	mac_out1 : stratixii_mac_out
		WITH (
			dataa_width = 16,
			dataout_width = 144,
			operation_mode = "output_only"
		);
	aclr	: NODE;
	clken	: NODE;

BEGIN 
	mac_mult2.aclr[] = aclr;
	mac_mult2.clk[] = clock;
	mac_mult2.dataa[] = ( dataa[]);
	mac_mult2.datab[] = ( datab[]);
	mac_mult2.ena[] = clken;
	mac_mult2.signa = B"0";
	mac_mult2.signb = B"0";
	mac_out1.aclr[] = aclr;
	mac_out1.clk[] = clock;
	mac_out1.dataa[] = ( mac_mult2.dataout[15..0]);
	mac_out1.ena[] = clken;
	mac_out1.signa = B"0";
	mac_out1.signb = B"0";
	aclr = GND;
	clken = VCC;
	result[15..0] = mac_out1.dataout[15..0];
END;
--VALID FILE