pipemult_lc_new.tan.qmsg

使用Quartus II 5.0开发指导手册

{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 q\[9\] ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0 7.588 ns memory " "Info: tco from clock \"clk1\" to destination pin \"q\[9\]\" through memory \"ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0\" is 7.588 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.387 ns + Longest memory " "Info: + Longest clock path from clock \"clk1\" to source memory is 2.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 79 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 79; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.471 ns) 2.387 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M512_X4_Y26 16 " "Info: 3: + IC(0.719 ns) + CELL(0.471 ns) = 2.387 ns; Loc. = M512_X4_Y26; Fanout = 16; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.190 ns" { clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.325 ns 55.51 % " "Info: Total cell delay = 1.325 ns ( 55.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.062 ns 44.49 % " "Info: Total interconnect delay = 1.062 ns ( 44.49 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.387 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.387 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 0.719ns } { 0.000ns 0.854ns 0.000ns 0.471ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.140 ns + " "Info: + Micro clock to output delay of source is 0.140 ns" {  } { { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.061 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M512_X4_Y26 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X4_Y26; Fanout = 16; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.793 ns) 1.793 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|q_b\[9\] 2 MEM M512_X4_Y26 1 " "Info: 2: + IC(0.000 ns) + CELL(1.793 ns) = 1.793 ns; Loc. = M512_X4_Y26; Fanout = 1; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|q_b\[9\]'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.793 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.280 ns) + CELL(1.988 ns) 5.061 ns q\[9\] 3 PIN PIN_D13 0 " "Info: 3: + IC(1.280 ns) + CELL(1.988 ns) = 5.061 ns; Loc. = PIN_D13; Fanout = 0; PIN Node = 'q\[9\]'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "3.268 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] q[9] } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 296 688 864 312 "q\[15..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.781 ns 74.71 % " "Info: Total cell delay = 3.781 ns ( 74.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.280 ns 25.29 % " "Info: Total interconnect delay = 1.280 ns ( 25.29 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "5.061 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] q[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.061 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] q[9] } { 0.000ns 0.000ns 1.280ns } { 0.000ns 1.793ns 1.988ns } } }  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.387 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.387 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 0.719ns } { 0.000ns 0.854ns 0.000ns 0.471ns } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "5.061 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] q[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.061 ns" { ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg0 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] q[9] } { 0.000ns 0.000ns 1.280ns } { 0.000ns 1.793ns 1.988ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "mult:inst\|lpm_mult:lpm_mult_component\|mult_0cr:auto_generated\|alt_mac_mult:mac_mult2\|datab_n\[5\] datab\[5\] clk1 -1.935 ns register " "Info: th for register \"mult:inst\|lpm_mult:lpm_mult_component\|mult_0cr:auto_generated\|alt_mac_mult:mac_mult2\|datab_n\[5\]\" (data pin = \"datab\[5\]\", clock pin = \"clk1\") is -1.935 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.480 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 2.480 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 79 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 79; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_new_cmp.qrpt" Compiler "pipemult_lc_new" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" {