pipemult_lc_phys_syn.fit.qmsg

使用Quartus II 5.0开发指导手册

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 27 17:07:29 2005 " "Info: Processing started: Fri May 27 17:07:29 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off pipemult -c pipemult_lc_phys_syn " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pipemult -c pipemult_lc_phys_syn" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "pipemult_lc_phys_syn EP2S15F484C3 " "Info: Selected device EP2S15F484C3 for design \"pipemult_lc_phys_syn\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S30F484C3 " "Info: Device EP2S30F484C3 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S60F484C3 " "Info: Device EP2S60F484C3 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S60F484C3ES " "Info: Device EP2S60F484C3ES is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk1 (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk1 (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0}  } { { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_phys_syn_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_phys_syn_cmp.qrpt" Compiler "pipemult_lc_phys_syn" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult_lc_phys_syn.fld" "" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult_lc_phys_syn.fld" "" "" { clk1 } "NODE_NAME" } }  } 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 0}