pipemult.map.qmsg

使用Quartus II 5.0开发指导手册

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 27 17:03:04 2005 " "Info: Processing started: Fri May 27 17:03:04 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pipemult -c pipemult " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pipemult -c pipemult" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram-rtl " "Info: Found design unit 1: ram-rtl" {  } { { "ram.vhd" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ram " "Info: Found entity 1: ram" {  } { { "ram.vhd" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pipemult.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pipemult.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pipemult " "Info: Found entity 1: pipemult" {  } { { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pipemult " "Info: Elaborating entity \"pipemult\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram ram:inst1 " "Info: Elaborating entity \"ram\" for hierarchy \"ram:inst1\"" {  } { { "pipemult.bdf" "inst1" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 272 504 672 400 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "mult.v 1 1 " "Info: Using design file mult.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mult " "Info: Found entity 1: mult" {  } { { "mult.v" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/mult.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult mult:inst " "Info: Elaborating entity \"mult\" for hierarchy \"mult:inst\"" {  } { { "pipemult.bdf" "inst" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 96 240 408 208 "inst" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_mult.tdf" 274 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult mult:inst\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"mult:inst\|lpm_mult:lpm_mult_component\"" {  } { { "mult.v" "lpm_mult_component" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/mult.v" 57 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_edq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_edq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_edq " "Info: Found entity 1: mult_edq" {  } { { "db/mult_edq.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/mult_edq.tdf" 36 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_edq mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated " "Info: Elaborating entity \"mult_edq\" for hierarchy \"mult:inst\|lpm_mult:lpm_mult_component\|mult_edq:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_mult.tdf" 343 3 0 } }  } 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_MRAM" "ram:inst1\|ram_block~5 " "Warning: Created node \"ram:inst1\|ram_block~5\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality may differ from the original design" {  } { { "ram.vhd" "ram_block~5" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 20 -1 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "ram:inst1\|ram_block~5 32 16 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=16) from the following design logic: \"ram:inst1\|ram_block~5\"" {  } { { "ram.vhd" "ram_block~5" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1p51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1p51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1p51 " "Info: Found entity 1: altsyncram_1p51" {  } { { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "66 " "Info: Implemented 66 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "28 " "Info: Implemented 28 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "5 " "Info: Implemented 5 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0} { "Info" "ISCL_SCL_TM_DSP_ELEM" "1 " "Info: Implemented 1 DSP elements" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 27 17:03:06 2005 " "Info: Processing ended: Fri May 27 17:03:06 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}