pipemult.fit.qmsg

使用Quartus II 5.0开发指导手册

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk1 (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk1 (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0}  } { { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.fld" "" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.fld" "" "" { clk1 } "NODE_NAME" } }  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0}