pipemult_lc_new.hier_info

使用Quartus II 5.0开发指导手册

|pipemult
q[0] <= ram:inst1.q[0]
q[1] <= ram:inst1.q[1]
q[2] <= ram:inst1.q[2]
q[3] <= ram:inst1.q[3]
q[4] <= ram:inst1.q[4]
q[5] <= ram:inst1.q[5]
q[6] <= ram:inst1.q[6]
q[7] <= ram:inst1.q[7]
q[8] <= ram:inst1.q[8]
q[9] <= ram:inst1.q[9]
q[10] <= ram:inst1.q[10]
q[11] <= ram:inst1.q[11]
q[12] <= ram:inst1.q[12]
q[13] <= ram:inst1.q[13]
q[14] <= ram:inst1.q[14]
q[15] <= ram:inst1.q[15]
clk1 => ram:inst1.clock
clk1 => mult:inst.clock
wren => ram:inst1.wren
dataa[0] => mult:inst.dataa[0]
dataa[1] => mult:inst.dataa[1]
dataa[2] => mult:inst.dataa[2]
dataa[3] => mult:inst.dataa[3]
dataa[4] => mult:inst.dataa[4]
dataa[5] => mult:inst.dataa[5]
dataa[6] => mult:inst.dataa[6]
dataa[7] => mult:inst.dataa[7]
datab[0] => mult:inst.datab[0]
datab[1] => mult:inst.datab[1]
datab[2] => mult:inst.datab[2]
datab[3] => mult:inst.datab[3]
datab[4] => mult:inst.datab[4]
datab[5] => mult:inst.datab[5]
datab[6] => mult:inst.datab[6]
datab[7] => mult:inst.datab[7]
rdaddress[0] => ram:inst1.rdaddress[0]
rdaddress[1] => ram:inst1.rdaddress[1]
rdaddress[2] => ram:inst1.rdaddress[2]
rdaddress[3] => ram:inst1.rdaddress[3]
rdaddress[4] => ram:inst1.rdaddress[4]
wraddress[0] => ram:inst1.wraddress[0]
wraddress[1] => ram:inst1.wraddress[1]
wraddress[2] => ram:inst1.wraddress[2]
wraddress[3] => ram:inst1.wraddress[3]
wraddress[4] => ram:inst1.wraddress[4]


|pipemult|ram:inst1
clock => q[15]~reg0.CLK
clock => q[14]~reg0.CLK
clock => q[13]~reg0.CLK
clock => q[12]~reg0.CLK
clock => q[11]~reg0.CLK
clock => q[10]~reg0.CLK
clock => q[9]~reg0.CLK
clock => q[8]~reg0.CLK
clock => q[7]~reg0.CLK
clock => q[6]~reg0.CLK
clock => q[5]~reg0.CLK
clock => q[4]~reg0.CLK
clock => q[3]~reg0.CLK
clock => q[2]~reg0.CLK
clock => q[1]~reg0.CLK
clock => q[0]~reg0.CLK
clock => ram_block.CLK0
clock => ram_block.CLK1
data[0] => ram_block.DATAIN
data[1] => ram_block.DATAIN1
data[2] => ram_block.DATAIN2
data[3] => ram_block.DATAIN3
data[4] => ram_block.DATAIN4
data[5] => ram_block.DATAIN5
data[6] => ram_block.DATAIN6
data[7] => ram_block.DATAIN7
data[8] => ram_block.DATAIN8
data[9] => ram_block.DATAIN9
data[10] => ram_block.DATAIN10
data[11] => ram_block.DATAIN11
data[12] => ram_block.DATAIN12
data[13] => ram_block.DATAIN13
data[14] => ram_block.DATAIN14
data[15] => ram_block.DATAIN15
wraddress[0] => ram_block.WADDR
wraddress[1] => ram_block.WADDR1
wraddress[2] => ram_block.WADDR2
wraddress[3] => ram_block.WADDR3
wraddress[4] => ram_block.WADDR4
rdaddress[0] => ram_block.RADDR
rdaddress[1] => ram_block.RADDR1
rdaddress[2] => ram_block.RADDR2
rdaddress[3] => ram_block.RADDR3
rdaddress[4] => ram_block.RADDR4
wren => ram_block.WE
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[10] <= q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[11] <= q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[12] <= q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[13] <= q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[14] <= q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[15] <= q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pipemult|mult:inst
dataa[0] => dataa[0]~7.IN1
dataa[1] => dataa[1]~6.IN1
dataa[2] => dataa[2]~5.IN1
dataa[3] => dataa[3]~4.IN1
dataa[4] => dataa[4]~3.IN1
dataa[5] => dataa[5]~2.IN1
dataa[6] => dataa[6]~1.IN1
dataa[7] => dataa[7]~0.IN1
datab[0] => datab[0]~7.IN1
datab[1] => datab[1]~6.IN1
datab[2] => datab[2]~5.IN1
datab[3] => datab[3]~4.IN1
datab[4] => datab[4]~3.IN1
datab[5] => datab[5]~2.IN1
datab[6] => datab[6]~1.IN1
datab[7] => datab[7]~0.IN1
clock => clock~0.IN1
result[0] <= lpm_mult:lpm_mult_component.result
result[1] <= lpm_mult:lpm_mult_component.result
result[2] <= lpm_mult:lpm_mult_component.result
result[3] <= lpm_mult:lpm_mult_component.result
result[4] <= lpm_mult:lpm_mult_component.result
result[5] <= lpm_mult:lpm_mult_component.result
result[6] <= lpm_mult:lpm_mult_component.result
result[7] <= lpm_mult:lpm_mult_component.result
result[8] <= lpm_mult:lpm_mult_component.result
result[9] <= lpm_mult:lpm_mult_component.result
result[10] <= lpm_mult:lpm_mult_component.result
result[11] <= lpm_mult:lpm_mult_component.result
result[12] <= lpm_mult:lpm_mult_component.result
result[13] <= lpm_mult:lpm_mult_component.result
result[14] <= lpm_mult:lpm_mult_component.result
result[15] <= lpm_mult:lpm_mult_component.result


|pipemult|mult:inst|lpm_mult:lpm_mult_component
dataa[0] => mult_0cr:auto_generated.dataa[0]
dataa[1] => mult_0cr:auto_generated.dataa[1]
dataa[2] => mult_0cr:auto_generated.dataa[2]
dataa[3] => mult_0cr:auto_generated.dataa[3]
dataa[4] => mult_0cr:auto_generated.dataa[4]
dataa[5] => mult_0cr:auto_generated.dataa[5]
dataa[6] => mult_0cr:auto_generated.dataa[6]
dataa[7] => mult_0cr:auto_generated.dataa[7]
datab[0] => mult_0cr:auto_generated.datab[0]
datab[1] => mult_0cr:auto_generated.datab[1]
datab[2] => mult_0cr:auto_generated.datab[2]
datab[3] => mult_0cr:auto_generated.datab[3]
datab[4] => mult_0cr:auto_generated.datab[4]
datab[5] => mult_0cr:auto_generated.datab[5]
datab[6] => mult_0cr:auto_generated.datab[6]
datab[7] => mult_0cr:auto_generated.datab[7]
sum[0] => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clock => mult_0cr:auto_generated.clock
clken => ~NO_FANOUT~
result[0] <= mult_0cr:auto_generated.result[0]
result[1] <= mult_0cr:auto_generated.result[1]
result[2] <= mult_0cr:auto_generated.result[2]
result[3] <= mult_0cr:auto_generated.result[3]
result[4] <= mult_0cr:auto_generated.result[4]
result[5] <= mult_0cr:auto_generated.result[5]
result[6] <= mult_0cr:auto_generated.result[6]
result[7] <= mult_0cr:auto_generated.result[7]
result[8] <= mult_0cr:auto_generated.result[8]
result[9] <= mult_0cr:auto_generated.result[9]
result[10] <= mult_0cr:auto_generated.result[10]
result[11] <= mult_0cr:auto_generated.result[11]
result[12] <= mult_0cr:auto_generated.result[12]
result[13] <= mult_0cr:auto_generated.result[13]
result[14] <= mult_0cr:auto_generated.result[14]
result[15] <= mult_0cr:auto_generated.result[15]


|pipemult|mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated
clock => mac_mult2.CLK
clock => mac_mult2.CLK1
clock => mac_mult2.CLK2
clock => mac_mult2.CLK3
clock => mac_out1.CLK
clock => mac_out1.CLK1
clock => mac_out1.CLK2
clock => mac_out1.CLK3
dataa[0] => mac_mult2.DATAA
dataa[1] => mac_mult2.DATAA1
dataa[2] => mac_mult2.DATAA2
dataa[3] => mac_mult2.DATAA3
dataa[4] => mac_mult2.DATAA4
dataa[5] => mac_mult2.DATAA5
dataa[6] => mac_mult2.DATAA6
dataa[7] => mac_mult2.DATAA7
datab[0] => mac_mult2.DATAB
datab[1] => mac_mult2.DATAB1
datab[2] => mac_mult2.DATAB2
datab[3] => mac_mult2.DATAB3
datab[4] => mac_mult2.DATAB4
datab[5] => mac_mult2.DATAB5
datab[6] => mac_mult2.DATAB6
datab[7] => mac_mult2.DATAB7
result[0] <= mac_out1.DATAOUT
result[1] <= mac_out1.DATAOUT1
result[2] <= mac_out1.DATAOUT2
result[3] <= mac_out1.DATAOUT3
result[4] <= mac_out1.DATAOUT4
result[5] <= mac_out1.DATAOUT5
result[6] <= mac_out1.DATAOUT6
result[7] <= mac_out1.DATAOUT7
result[8] <= mac_out1.DATAOUT8
result[9] <= mac_out1.DATAOUT9
result[10] <= mac_out1.DATAOUT10
result[11] <= mac_out1.DATAOUT11
result[12] <= mac_out1.DATAOUT12
result[13] <= mac_out1.DATAOUT13
result[14] <= mac_out1.DATAOUT14
result[15] <= mac_out1.DATAOUT15