pipemult_lc.tan.qmsg

来自「使用Quartus II 5.0开发指导手册」· QMSG 代码 · 共 6 行 · 第 1/5 页

{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'clk1' 56 " "Warning: Can't achieve timing requirement Clock Setup: 'clk1' along 56 path(s). See Report window for details." {  } {  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk1 register ram:inst1\|ram_block~1 memory ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg1 436 ps " "Info: Minimum slack time is 436 ps for clock \"clk1\" between source register \"ram:inst1\|ram_block~1\" and destination memory \"ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg1\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.445 ns + Shortest register memory " "Info: + Shortest register to memory delay is 0.445 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram:inst1\|ram_block~1 1 REG LCFF_X3_Y24_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X3_Y24_N3; Fanout = 1; REG Node = 'ram:inst1\|ram_block~1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { ram:inst1|ram_block~1 } "NODE_NAME" } "" } } { "ram.vhd" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.129 ns) 0.445 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg1 2 MEM M512_X4_Y24 16 " "Info: 2: + IC(0.316 ns) + CELL(0.129 ns) = 0.445 ns; Loc. = M512_X4_Y24; Fanout = 16; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.445 ns" { ram:inst1|ram_block~1 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.129 ns 28.99 % " "Info: Total cell delay = 0.129 ns ( 28.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.316 ns 71.01 % " "Info: Total interconnect delay = 0.316 ns ( 71.01 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.445 ns" { ram:inst1|ram_block~1 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.445 ns" { ram:inst1|ram_block~1 ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } { 0.0ns 0.316ns } { 0.0ns 0.129ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.009 ns - Smallest register memory " "Info: - Smallest register to memory requirement is 0.009 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk1 4.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk1\" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk1 4.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk1\" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.100 ns + Smallest " "Info: + Smallest clock skew is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.383 ns + Longest memory " "Info: + Longest clock path from clock \"clk1\" to destination memory is 2.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 79 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 79; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.715 ns) + CELL(0.471 ns) 2.383 ns ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg1 3 MEM M512_X4_Y24 16 " "Info: 3: + IC(0.715 ns) + CELL(0.471 ns) = 2.383 ns; Loc. = M512_X4_Y24; Fanout = 16; MEM Node = 'ram:inst1\|altsyncram:ram_block_rtl_0\|altsyncram_1p51:auto_generated\|ram_block1a0~portb_address_reg1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.186 ns" { clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.325 ns 55.60 % " "Info: Total cell delay = 1.325 ns ( 55.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.058 ns 44.40 % " "Info: Total interconnect delay = 1.058 ns ( 44.40 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.383 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.383 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } { 0.0ns 0.0ns 0.343ns 0.715ns } { 0.0ns 0.854ns 0.0ns 0.471ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.483 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to source register is 2.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk1 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "" { clk1 } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk1~clkctrl 2 COMB CLKCTRL_G3 79 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 79; COMB Node = 'clk1~clkctrl'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "0.343 ns" { clk1 clk1~clkctrl } "NODE_NAME" } "" } } { "pipemult.bdf" "" { Schematic "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.bdf" { { 120 56 224 136 "clk1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.618 ns) 2.483 ns ram:inst1\|ram_block~1 3 REG LCFF_X3_Y24_N3 1 " "Info: 3: + IC(0.668 ns) + CELL(0.618 ns) = 2.483 ns; Loc. = LCFF_X3_Y24_N3; Fanout = 1; REG Node = 'ram:inst1\|ram_block~1'" {  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "1.286 ns" { clk1~clkctrl ram:inst1|ram_block~1 } "NODE_NAME" } "" } } { "ram.vhd" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns 59.28 % " "Info: Total cell delay = 1.472 ns ( 59.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.011 ns 40.72 % " "Info: Total interconnect delay = 1.011 ns ( 40.72 % )" {  } {  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.483 ns" { clk1 clk1~clkctrl ram:inst1|ram_block~1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.483 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|ram_block~1 } { 0.0ns 0.0ns 0.343ns 0.668ns } { 0.0ns 0.854ns 0.0ns 0.618ns } } }  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.383 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.383 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } { 0.0ns 0.0ns 0.343ns 0.715ns } { 0.0ns 0.854ns 0.0ns 0.471ns } } } { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.483 ns" { clk1 clk1~clkctrl ram:inst1|ram_block~1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.483 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|ram_block~1 } { 0.0ns 0.0ns 0.343ns 0.668ns } { 0.0ns 0.854ns 0.0ns 0.618ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" {  } { { "ram.vhd" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/ram.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.203 ns + " "Info: + Micro hold delay of destination is 0.203 ns" {  } { { "db/altsyncram_1p51.tdf" "" { Text "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/altsyncram_1p51.tdf" 45 2 0 } }  } 0}  } { { "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" "" { Report "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult_lc_cmp.qrpt" Compiler "pipemult_lc" "UNKNOWN" "V1" "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/db/pipemult.quartus_db" { Floorplan "D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/" "" "2.383 ns" { clk1 clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.383 ns" { clk1 clk1~combout clk1~clkctrl ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_