📄 pipemult.map.rpt
字号:
; CARRY_CHAIN ; MANUAL ; Untyped ;
; APEX20K_TECHNOLOGY_MAPPER ; Lut ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; CBXI_PARAMETER ; mult_edq ; Untyped ;
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
+------------------------------------------------+------------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: ram:inst1|altsyncram:ram_block_rtl_0 ;
+------------------------------------+-----------------+--------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-----------------+--------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 16 ; Untyped ;
; WIDTHAD_A ; 5 ; Untyped ;
; NUMWORDS_A ; 32 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 16 ; Untyped ;
; WIDTHAD_B ; 5 ; Untyped ;
; NUMWORDS_B ; 32 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Stratix II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_1p51 ; Untyped ;
+------------------------------------+-----------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+---------------------------------------+
; Name ; Value ;
+---------------------------------------+---------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; mult:inst|lpm_mult:lpm_mult_component ;
; -- LPM_WIDTHA ; 8 ;
; -- LPM_WIDTHB ; 8 ;
; -- LPM_WIDTHP ; 16 ;
; -- LPM_REPRESENTATION ; UNSIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+---------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Training/Designing_with_Quartus_II_v5_0/QII5_0/Lab1_6/pipemult.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Fri May 27 17:03:04 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pipemult -c pipemult
Info: Found 2 design units, including 1 entities, in source file ram.vhd
Info: Found design unit 1: ram-rtl
Info: Found entity 1: ram
Info: Found 1 design units, including 1 entities, in source file pipemult.bdf
Info: Found entity 1: pipemult
Info: Elaborating entity "pipemult" for the top level hierarchy
Info: Elaborating entity "ram" for hierarchy "ram:inst1"
Info: Using design file mult.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: mult
Info: Elaborating entity "mult" for hierarchy "mult:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_mult.tdf
Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "mult:inst|lpm_mult:lpm_mult_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_edq.tdf
Info: Found entity 1: mult_edq
Info: Elaborating entity "mult_edq" for hierarchy "mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated"
Warning: Created node "ram:inst1|ram_block~5" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality may differ from the original design
Info: Inferred 1 megafunctions from design logic
Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=16) from the following design logic: "ram:inst1|ram_block~5"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1p51.tdf
Info: Found entity 1: altsyncram_1p51
Info: Implemented 66 device resources after synthesis - the final resource count might be different
Info: Implemented 28 input pins
Info: Implemented 16 output pins
Info: Implemented 5 logic cells
Info: Implemented 16 RAM segments
Info: Implemented 1 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Processing ended: Fri May 27 17:03:06 2005
Info: Elapsed time: 00:00:03
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -