pipemult_lc.tan.rpt

来自「使用Quartus II 5.0开发指导手册」· RPT 代码 · 共 228 行 · 第 1/5 页

; Worst-case tco               ; N/A       ; None                             ; 7.626 ns                         ; ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg4 ; q[9]                                                                                                ; clk1       ;          ; 0            ;
; Worst-case th                ; N/A       ; None                             ; 0.899 ns                         ; dataa[2]                                                                                            ; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[2]     ;            ; clk1     ; 0            ;
; Clock Setup: 'clk1'          ; -0.477 ns ; 250.00 MHz ( period = 4.000 ns ) ; 223.36 MHz ( period = 4.477 ns ) ; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[1]     ; mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[15]  ; clk1       ; clk1     ; 56           ;
; Clock Hold: 'clk1'           ; 0.436 ns  ; 250.00 MHz ( period = 4.000 ns ) ; N/A                              ; ram:inst1|ram_block~1                                                                               ; ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|ram_block1a0~portb_address_reg1 ; clk1       ; clk1     ; 0            ;
; Total number of failed paths ;           ;                                  ;                                  ;                                                                                                     ;                                                                                                     ;            ;          ; 56           ;
+------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                ;
+-------------------------------------------------------+--------------------+------+-------+-------------+
; Option                                                ; Setting            ; From ; To    ; Entity Name ;
+-------------------------------------------------------+--------------------+------+-------+-------------+
; Device Name                                           ; EP2S15F484C3       ;      ;       ;             ;
; Timing Models                                         ; Preliminary        ;      ;       ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;       ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;       ;             ;
; Number of paths to report                             ; 200                ;      ;       ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;       ;             ;
; Use Fast Timing Models                                ; Off                ;      ;       ;             ;
; Report IO Paths Separately                            ; Off                ;      ;       ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;       ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;       ;             ;
; Cut off read during write signal paths                ; On                 ;      ;       ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;       ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;       ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;       ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;       ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;       ;             ;
; Enable Clock Latency                                  ; Off                ;      ;       ;             ;
; Clock Settings                                        ; clk1               ;      ; clk1  ;             ;
; Input Maximum Delay                                   ; 3.5ns              ; *    ; data* ;             ;
+-------------------------------------------------------+--------------------+------+-------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk1            ; clk1               ; User Pin ; 250.0 MHz        ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk1'                                                                                                                                                                                                                                                                                                                                                                                              ;