pipemult_lc_phys_syn.fit.eqn

来自「使用Quartus II 5.0开发指导手册」· EQN 代码 · 共 948 行 · 第 1/5 页

K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L4Q, C1L6Q, C1L8Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[14] = K1_q_b[0]_PORT_B_data_out[14];

--K1_q_b[13] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[13] at M512_X4_Y23
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], H1L2, H1L01, H1L81, H1L82, H1L83, H1L84, H1L85, H1L86, H1L87, H1L78, H1L89, H1L901, H1L021, H1L821);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L4Q, C1L6Q, C1L8Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[13] = K1_q_b[0]_PORT_B_data_out[13];

--K1_q_b[12] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[12] at M512_X4_Y23
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], H1L2, H1L01, H1L81, H1L82, H1L83, H1L84, H1L85, H1L86, H1L87, H1L78, H1L89, H1L901, H1L021, H1L821);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L4Q, C1L6Q, C1L8Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[12] = K1_q_b[0]_PORT_B_data_out[12];

--K1_q_b[11] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[11] at M512_X4_Y23
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], H1L2, H1L01, H1L81, H1L82, H1L83, H1L84, H1L85, H1L86, H1L87, H1L78, H1L89, H1L901, H1L021, H1L821);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L4Q, C1L6Q, C1L8Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[11] = K1_q_b[0]_PORT_B_data_out[11];

--K1_q_b[10] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[10] at M512_X4_Y23
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], H1L2, H1L01, H1L81, H1L82, H1L83, H1L84, H1L85, H1L86, H1L87, H1L78, H1L89, H1L901, H1L021, H1L821);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L4Q, C1L6Q, C1L8Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[10] = K1_q_b[0]_PORT_B_data_out[10];

--K1_q_b[9] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] at M512_X4_Y23
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], H1L2, H1L01, H1L81, H1L82, H1L83, H1L84, H1L85, H1L86, H1L87, H1L78, H1L89, H1L901, H1L021, H1L821);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L4Q, C1L6Q, C1L8Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[9] = K1_q_b[0]_PORT_B_data_out[9];


--C1L1Q is ram:inst1|ram_block~0 at LCFF_X3_Y23_N31
C1L1Q = DFFEAS(C1L2, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L3Q is ram:inst1|ram_block~1 at LCFF_X2_Y23_N23
C1L3Q = DFFEAS( , GLOBAL(A1L2),  ,  ,  , rdaddress[1],  ,  , VCC);


--C1L4Q is ram:inst1|ram_block~2 at LCFF_X3_Y23_N21
C1L4Q = DFFEAS(C1L5, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L6Q is ram:inst1|ram_block~3 at LCFF_X3_Y23_N23
C1L6Q = DFFEAS(C1L7, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L8Q is ram:inst1|ram_block~4 at LCFF_X3_Y23_N27
C1L8Q = DFFEAS( , GLOBAL(A1L2),  ,  ,  , rdaddress[4],  ,  , VCC);


--F1_dataout_n[1] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[1] at LCFF_X2_Y23_N1
F1_dataout_n[1] = DFFEAS(H1L002, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[0] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[0] at LCFF_X2_Y23_N31
F1_dataout_n[0] = DFFEAS(H1_w_decoder_node9w[0], GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataa_n[7] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[7] at LCFF_X2_Y23_N27
F1_dataa_n[7] = DFFEAS(F1L21, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_datab_n[7] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|datab_n[7] at LCFF_X1_Y24_N5
F1_datab_n[7] = DFFEAS( , GLOBAL(A1L2),  ,  ,  , datab[7],  ,  , VCC);


--F1_dataa_n[6] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[6] at LCFF_X1_Y24_N11
F1_dataa_n[6] = DFFEAS( , GLOBAL(A1L2),  ,  ,  , dataa[6],  ,  , VCC);


--F1_datab_n[6] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|datab_n[6] at LCFF_X1_Y26_N19
F1_datab_n[6] = DFFEAS( , GLOBAL(A1L2),  ,  ,  , datab[6],  ,  , VCC);


--F1_dataa_n[5] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[5] at LCFF_X1_Y23_N21
F1_dataa_n[5] = DFFEAS(F1L9, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataa_n[4] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[4] at LCFF_X2_Y23_N19
F1_dataa_n[4] = DFFEAS( , GLOBAL(A1L2),  ,  ,  , dataa[4],  ,  , VCC);


--F1_dataa_n[3] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[3] at LCFF_X2_Y24_N5
F1_dataa_n[3] = DFFEAS( , GLOBAL(A1L2),  ,  ,  , dataa[3],  ,  , VCC);


--F1_dataa_n[2] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[2] at LCFF_X2_Y24_N3
F1_dataa_n[2] = DFFEAS( , GLOBAL(A1L2),  ,  ,  , dataa[2],  ,  , VCC);


--F1_dataa_n[1] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[1] at LCFF_X1_Y23_N29
F1_dataa_n[1] = DFFEAS(F1L4, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataa_n[0] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataa_n[0] at LCFF_X1_Y24_N1
F1_dataa_n[0] = DFFEAS( , GLOBAL(A1L2),  ,  ,  , dataa[0],  ,  , VCC);


--H1L803 is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|op_10~49 at LCCOMB_X1_Y24_N0
H1L803_adder_eqn = ( F1_dataa_n[1] & F1_datab_n[6] ) + ( F1_dataa_n[0] & F1_datab_n[7] ) + ( GND );
H1L803 = SUM(H1L803_adder_eqn);

--H1L903 is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|op_10~50 at LCCOMB_X1_Y24_N0
H1L903_adder_eqn = ( F1_dataa_n[1] & F1_datab_n[6] ) + ( F1_dataa_n[0] & F1_datab_n[7] ) + ( GND );
H1L903 = CARRY(H1L903_adder_eqn);


--H1L213 is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|op_10~53 at LCCOMB_X1_Y24_N2
H1L213_adder_eqn = ( F1_dataa_n[2] & F1_datab_n[6] ) + ( F1_dataa_n[1] & F1_datab_n[7] ) + ( H1L903 );
H1L213 = SUM(H1L213_adder_eqn);

--H1L313 is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|op_10~54 at LCCOMB_X1_Y24_N2
H1L313_adder_eqn = ( F1_dataa_n[2] & F1_datab_n[6] ) + ( F1_dataa_n[1] & F1_datab_n[7] ) + ( H1L903 );
H1L313 = CARRY(H1L313_adder_eqn);


--H1L613 is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|lpm_mult:mult|mult_tf71:auto_generated|op_10~57 at LCCOMB_X1_Y24_N4
H1L613_adder_eqn = ( F1_dataa_n[2] & F1_datab_n[7] ) + ( F1_dataa_n[3] & F1_datab_n[6] ) + ( H1L313 );
H1L613 = SUM(H1L613_adder_eqn);