pipemult_lc_02.fit.eqn

使用Quartus II 5.0开发指导手册

K1_q_b[15] = K1_q_b[0]_PORT_B_data_out[15];

--K1_q_b[14] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[14] at M512_X4_Y26
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], F1_dataout_n[2], F1_dataout_n[3], F1_dataout_n[4], F1_dataout_n[5], F1_dataout_n[6], F1_dataout_n[7], F1_dataout_n[8], F1_dataout_n[9], F1_dataout_n[10], F1_dataout_n[11], F1_dataout_n[12], F1_dataout_n[13], F1_dataout_n[14], F1_dataout_n[15]);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L5Q, C1L7Q, C1L9Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[14] = K1_q_b[0]_PORT_B_data_out[14];

--K1_q_b[13] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[13] at M512_X4_Y26
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], F1_dataout_n[2], F1_dataout_n[3], F1_dataout_n[4], F1_dataout_n[5], F1_dataout_n[6], F1_dataout_n[7], F1_dataout_n[8], F1_dataout_n[9], F1_dataout_n[10], F1_dataout_n[11], F1_dataout_n[12], F1_dataout_n[13], F1_dataout_n[14], F1_dataout_n[15]);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L5Q, C1L7Q, C1L9Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[13] = K1_q_b[0]_PORT_B_data_out[13];

--K1_q_b[12] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[12] at M512_X4_Y26
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], F1_dataout_n[2], F1_dataout_n[3], F1_dataout_n[4], F1_dataout_n[5], F1_dataout_n[6], F1_dataout_n[7], F1_dataout_n[8], F1_dataout_n[9], F1_dataout_n[10], F1_dataout_n[11], F1_dataout_n[12], F1_dataout_n[13], F1_dataout_n[14], F1_dataout_n[15]);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L5Q, C1L7Q, C1L9Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[12] = K1_q_b[0]_PORT_B_data_out[12];

--K1_q_b[11] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[11] at M512_X4_Y26
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], F1_dataout_n[2], F1_dataout_n[3], F1_dataout_n[4], F1_dataout_n[5], F1_dataout_n[6], F1_dataout_n[7], F1_dataout_n[8], F1_dataout_n[9], F1_dataout_n[10], F1_dataout_n[11], F1_dataout_n[12], F1_dataout_n[13], F1_dataout_n[14], F1_dataout_n[15]);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L5Q, C1L7Q, C1L9Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[11] = K1_q_b[0]_PORT_B_data_out[11];

--K1_q_b[10] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[10] at M512_X4_Y26
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], F1_dataout_n[2], F1_dataout_n[3], F1_dataout_n[4], F1_dataout_n[5], F1_dataout_n[6], F1_dataout_n[7], F1_dataout_n[8], F1_dataout_n[9], F1_dataout_n[10], F1_dataout_n[11], F1_dataout_n[12], F1_dataout_n[13], F1_dataout_n[14], F1_dataout_n[15]);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L5Q, C1L7Q, C1L9Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[10] = K1_q_b[0]_PORT_B_data_out[10];

--K1_q_b[9] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] at M512_X4_Y26
K1_q_b[0]_PORT_A_data_in = BUS(F1_dataout_n[0], F1_dataout_n[1], F1_dataout_n[2], F1_dataout_n[3], F1_dataout_n[4], F1_dataout_n[5], F1_dataout_n[6], F1_dataout_n[7], F1_dataout_n[8], F1_dataout_n[9], F1_dataout_n[10], F1_dataout_n[11], F1_dataout_n[12], F1_dataout_n[13], F1_dataout_n[14], F1_dataout_n[15]);
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L3Q, C1L5Q, C1L7Q, C1L9Q);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , );
K1_q_b[0]_clock_0 = GLOBAL(A1L2);
K1_q_b[0]_clock_1 = GLOBAL(A1L2);
K1_q_b[0]_clock_enable_0 = wren;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, , , );
K1_q_b[9] = K1_q_b[0]_PORT_B_data_out[9];


--F1_dataout_n[15] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[15] at LCFF_X3_Y25_N11
F1_dataout_n[15] = DFFEAS(H1L45, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L1Q is ram:inst1|ram_block~0 at LCFF_X3_Y24_N9
C1L1Q = DFFEAS(C1L2, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L3Q is ram:inst1|ram_block~1 at LCFF_X3_Y23_N9
C1L3Q = DFFEAS(C1L4, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L5Q is ram:inst1|ram_block~2 at LCFF_X1_Y21_N5
C1L5Q = DFFEAS(C1L6, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L7Q is ram:inst1|ram_block~3 at LCFF_X2_Y22_N17
C1L7Q = DFFEAS(C1L8, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L9Q is ram:inst1|ram_block~4 at LCFF_X3_Y21_N1
C1L9Q = DFFEAS(C1L01, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[14] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[14] at LCFF_X3_Y25_N9
F1_dataout_n[14] = DFFEAS(H1L05, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[13] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[13] at LCFF_X3_Y25_N7
F1_dataout_n[13] = DFFEAS(H1L64, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[12] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[12] at LCFF_X3_Y25_N5
F1_dataout_n[12] = DFFEAS(H1L24, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[11] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[11] at LCFF_X3_Y25_N3
F1_dataout_n[11] = DFFEAS(H1L83, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[10] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[10] at LCFF_X3_Y25_N1
F1_dataout_n[10] = DFFEAS(H1L43, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[9] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[9] at LCFF_X3_Y26_N31
F1_dataout_n[9] = DFFEAS(H1L03, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[8] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[8] at LCFF_X3_Y26_N29
F1_dataout_n[8] = DFFEAS(H1L62, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[7] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[7] at LCFF_X3_Y26_N27
F1_dataout_n[7] = DFFEAS(H1L22, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[6] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[6] at LCFF_X3_Y26_N25
F1_dataout_n[6] = DFFEAS(H1L81, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[5] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[5] at LCFF_X3_Y26_N23
F1_dataout_n[5] = DFFEAS(H1L41, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[4] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[4] at LCFF_X3_Y26_N21
F1_dataout_n[4] = DFFEAS(H1L01, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[3] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[3] at LCFF_X3_Y26_N19
F1_dataout_n[3] = DFFEAS(H1L6, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[2] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[2] at LCFF_X3_Y26_N17
F1_dataout_n[2] = DFFEAS(H1L2, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--F1_dataout_n[1] is mult:inst|lpm_mult:lpm_mult_component|mult_0cr:auto_generated|alt_mac_mult:mac_mult2|dataout_n[1] at LCFF_X2_Y24_N1
F1_dataout_n[1] = DFFEAS(H1L811, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );