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使用Quartus II 5.0开发指导手册

G1_q_b[12] = G1_q_b[0]_PORT_B_data_out[12];

--G1_q_b[11] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[11] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[11] = G1_q_b[0]_PORT_B_data_out[11];

--G1_q_b[10] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[10] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[10] = G1_q_b[0]_PORT_B_data_out[10];

--G1_q_b[9] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[9] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[9] = G1_q_b[0]_PORT_B_data_out[9];


--E1_result[0] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[0] at DSPOUT_X28_Y22_N2
--DSP Block Operation Mode: Simple Multiplier (9-bit)
E1_result[0] = E1_mac_mult2;

--E1_result[1] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[1] at DSPOUT_X28_Y22_N2
E1_result[1] = E1L8Q;

--E1_result[2] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[2] at DSPOUT_X28_Y22_N2
E1_result[2] = E1L9Q;

--E1_result[3] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[3] at DSPOUT_X28_Y22_N2
E1_result[3] = E1L01Q;

--E1_result[4] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[4] at DSPOUT_X28_Y22_N2
E1_result[4] = E1L11Q;

--E1_result[5] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[5] at DSPOUT_X28_Y22_N2
E1_result[5] = E1L21Q;

--E1_result[6] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[6] at DSPOUT_X28_Y22_N2
E1_result[6] = E1L31Q;

--E1_result[7] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[7] at DSPOUT_X28_Y22_N2
E1_result[7] = E1L41Q;

--E1_result[8] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[8] at DSPOUT_X28_Y22_N2
E1_result[8] = E1L51Q;

--E1_result[9] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[9] at DSPOUT_X28_Y22_N2
E1_result[9] = E1L61Q;

--E1_result[10] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[10] at DSPOUT_X28_Y22_N2
E1_result[10] = E1L71Q;

--E1_result[11] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[11] at DSPOUT_X28_Y22_N2
E1_result[11] = E1L81Q;

--E1_result[12] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[12] at DSPOUT_X28_Y22_N2
E1_result[12] = E1L91Q;

--E1_result[13] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[13] at DSPOUT_X28_Y22_N2
E1_result[13] = E1L02Q;

--E1_result[14] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[14] at DSPOUT_X28_Y22_N2
E1_result[14] = E1L12Q;

--E1_result[15] is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|result[15] at DSPOUT_X28_Y22_N2
E1_result[15] = E1L22Q;


--C1L1Q is ram:inst1|ram_block~0 at LCFF_X25_Y23_N13
C1L1Q = DFFEAS( , GLOBAL(A1L2),  ,  ,  , rdaddress[0],  ,  , VCC);


--C1L2Q is ram:inst1|ram_block~1 at LCFF_X25_Y22_N9
C1L2Q = DFFEAS(C1L3, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L4Q is ram:inst1|ram_block~2 at LCFF_X27_Y22_N1
C1L4Q = DFFEAS( , GLOBAL(A1L2),  ,  ,  , rdaddress[2],  ,  , VCC);


--C1L5Q is ram:inst1|ram_block~3 at LCFF_X23_Y22_N17
C1L5Q = DFFEAS(C1L6, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--C1L7Q is ram:inst1|ram_block~4 at LCFF_X26_Y22_N29
C1L7Q = DFFEAS(C1L8, GLOBAL(A1L2),  ,  ,  ,  ,  ,  ,  );


--E1_mac_mult2 is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2 at DSPMULT_X28_Y22_N0
--DSP Block Multiplier Base Width: 9-bits
E1_mac_mult2_a_data = DATA(dataa[7], dataa[6], dataa[5], dataa[4], dataa[3], dataa[2], dataa[1], dataa[0]);
E1_mac_mult2_a_reg = DFFE(E1_mac_mult2_a_data, GLOBAL(A1L2), , , );
E1_mac_mult2_a_rep = UNSIGNED(E1_mac_mult2_a_reg);
E1_mac_mult2_b_data = DATA(datab[7], datab[6], datab[5], datab[4], datab[3], datab[2], datab[1], datab[0]);
E1_mac_mult2_b_reg = DFFE(E1_mac_mult2_b_data, GLOBAL(A1L2), , , );
E1_mac_mult2_b_rep = UNSIGNED(E1_mac_mult2_b_reg);
E1_mac_mult2_result = E1_mac_mult2_a_rep * E1_mac_mult2_b_rep;
E1_mac_mult2_round = E1_mac_mult2_result;
E1_mac_mult2_saturate = E1_mac_mult2_round;
E1_mac_mult2_result_reg = DFFE(E1_mac_mult2_saturate, GLOBAL(A1L2), , , );
E1_mac_mult2 = E1_mac_mult2_result_reg[0];

--E1L8Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT1 at DSPMULT_X28_Y22_N0
E1L8Q = E1_mac_mult2_result_reg[1];

--E1L9Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT2 at DSPMULT_X28_Y22_N0
E1L9Q = E1_mac_mult2_result_reg[2];

--E1L01Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT3 at DSPMULT_X28_Y22_N0
E1L01Q = E1_mac_mult2_result_reg[3];

--E1L11Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT4 at DSPMULT_X28_Y22_N0
E1L11Q = E1_mac_mult2_result_reg[4];

--E1L21Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT5 at DSPMULT_X28_Y22_N0
E1L21Q = E1_mac_mult2_result_reg[5];

--E1L31Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT6 at DSPMULT_X28_Y22_N0
E1L31Q = E1_mac_mult2_result_reg[6];

--E1L41Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT7 at DSPMULT_X28_Y22_N0
E1L41Q = E1_mac_mult2_result_reg[7];

--E1L51Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT8 at DSPMULT_X28_Y22_N0
E1L51Q = E1_mac_mult2_result_reg[8];

--E1L61Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT9 at DSPMULT_X28_Y22_N0
E1L61Q = E1_mac_mult2_result_reg[9];

--E1L71Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT10 at DSPMULT_X28_Y22_N0
E1L71Q = E1_mac_mult2_result_reg[10];

--E1L81Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT11 at DSPMULT_X28_Y22_N0
E1L81Q = E1_mac_mult2_result_reg[11];

--E1L91Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT12 at DSPMULT_X28_Y22_N0
E1L91Q = E1_mac_mult2_result_reg[12];

--E1L02Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT13 at DSPMULT_X28_Y22_N0
E1L02Q = E1_mac_mult2_result_reg[13];

--E1L12Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT14 at DSPMULT_X28_Y22_N0
E1L12Q = E1_mac_mult2_result_reg[14];

--E1L22Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~DATAOUT15 at DSPMULT_X28_Y22_N0
E1L22Q = E1_mac_mult2_result_reg[15];

--E1L6Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~4 at DSPMULT_X28_Y22_N0
E1L6Q = GND;

--E1L7Q is mult:inst|lpm_mult:lpm_mult_component|mult_edq:auto_generated|mac_mult2~5 at DSPMULT_X28_Y22_N0
E1L7Q = GND;


--clk1 is clk1 at PIN_N20
--operation mode is input

clk1 = INPUT();


--wren is wren at PIN_D13
--operation mode is input

wren = INPUT();


--wraddress[0] is wraddress[0] at PIN_D12
--operation mode is input

wraddress[0] = INPUT();


--wraddress[1] is wraddress[1] at PIN_D10
--operation mode is input

wraddress[1] = INPUT();


--wraddress[2] is wraddress[2] at PIN_C11
--operation mode is input

wraddress[2] = INPUT();


--wraddress[3] is wraddress[3] at PIN_C12
--operation mode is input

wraddress[3] = INPUT();


--wraddress[4] is wraddress[4] at PIN_C13
--operation mode is input

wraddress[4] = INPUT();


--rdaddress[0] is rdaddress[0] at PIN_A10
--operation mode is input

rdaddress[0] = INPUT();