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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--G1_q_b[0] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[0] at M512_X24_Y22
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 16, Port B Depth: 32, Port B Width: 16
--Port A Logical Depth: 32, Port A Logical Width: 16, Port B Logical Depth: 32, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[0] = G1_q_b[0]_PORT_B_data_out[0];

--G1_q_b[8] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[8] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[8] = G1_q_b[0]_PORT_B_data_out[8];

--G1_q_b[7] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[7] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[7] = G1_q_b[0]_PORT_B_data_out[7];

--G1_q_b[6] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[6] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[6] = G1_q_b[0]_PORT_B_data_out[6];

--G1_q_b[5] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[5] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[5] = G1_q_b[0]_PORT_B_data_out[5];

--G1_q_b[4] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[4] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[4] = G1_q_b[0]_PORT_B_data_out[4];

--G1_q_b[3] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[3] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[3] = G1_q_b[0]_PORT_B_data_out[3];

--G1_q_b[2] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[2] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[2] = G1_q_b[0]_PORT_B_data_out[2];

--G1_q_b[1] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[1] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[1] = G1_q_b[0]_PORT_B_data_out[1];

--G1_q_b[15] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[15] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[15] = G1_q_b[0]_PORT_B_data_out[15];

--G1_q_b[14] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[14] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[14] = G1_q_b[0]_PORT_B_data_out[14];

--G1_q_b[13] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[13] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
G1_q_b[13] = G1_q_b[0]_PORT_B_data_out[13];

--G1_q_b[12] is ram:inst1|altsyncram:ram_block_rtl_0|altsyncram_1p51:auto_generated|q_b[12] at M512_X24_Y22
G1_q_b[0]_PORT_A_data_in = BUS(E1_result[0], E1_result[1], E1_result[2], E1_result[3], E1_result[4], E1_result[5], E1_result[6], E1_result[7], E1_result[8], E1_result[9], E1_result[10], E1_result[11], E1_result[12], E1_result[13], E1_result[14], E1_result[15]);
G1_q_b[0]_PORT_A_data_in_reg = DFFE(G1_q_b[0]_PORT_A_data_in, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_A_address = BUS(wraddress[0], wraddress[1], wraddress[2], wraddress[3], wraddress[4]);
G1_q_b[0]_PORT_A_address_reg = DFFE(G1_q_b[0]_PORT_A_address, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_address = BUS(C1L1Q, C1L2Q, C1L4Q, C1L5Q, C1L7Q);
G1_q_b[0]_PORT_B_address_reg = DFFE(G1_q_b[0]_PORT_B_address, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_PORT_A_write_enable = VCC;
G1_q_b[0]_PORT_A_write_enable_reg = DFFE(G1_q_b[0]_PORT_A_write_enable, G1_q_b[0]_clock_0, , , G1_q_b[0]_clock_enable_0);
G1_q_b[0]_PORT_B_read_enable = VCC;
G1_q_b[0]_PORT_B_read_enable_reg = DFFE(G1_q_b[0]_PORT_B_read_enable, G1_q_b[0]_clock_1, , , );
G1_q_b[0]_clock_0 = GLOBAL(A1L2);
G1_q_b[0]_clock_1 = GLOBAL(A1L2);
G1_q_b[0]_clock_enable_0 = wren;
G1_q_b[0]_PORT_B_data_out = MEMORY(G1_q_b[0]_PORT_A_data_in_reg, , G1_q_b[0]_PORT_A_address_reg, G1_q_b[0]_PORT_B_address_reg, G1_q_b[0]_PORT_A_write_enable_reg, G1_q_b[0]_PORT_B_read_enable_reg, , , G1_q_b[0]_clock_0, G1_q_b[0]_clock_1, G1_q_b[0]_clock_enable_0, , , );
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